 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004-2005, zarlink semiconductor inc. all rights reserved. features general ? circuit emulation services over packet (cesop) transport for mpls, ip and ethernet networks ? on chip timing & synchronization recovery across a packet network ? on chip dual reference stratum 3 dpll ? grooming capability for nx64 kbps trunking ? fully compatible with zarlink's zl50110, zl50111 and zl50114 cesop processors circuit emulation services ? complies with itu-t recommendation y.1413 ? complies with ietf pwe3 draft standards cesopsn and satop ? complies with cesop implementation agreements from mef 8 and mfa 8.0.0 ? structured, synchronous cesop with clock recovery ? unstructured, asynchronous cesop with integral per-stream clock recovery customer side tdm interfaces ? up to 4 t1/e1, 1 j2, 1 t3/e3, or 1 sts-1 ports ? h.110, h-mvip, st-bus backplane ? up to 128 bi-directional 64 kbps channels ? direct connection to lius, framers, backplanes customer side packet interfaces ? 100 mbps mii fast ethernet (zl50118/19/20 only) (may also be used as a second provider side packet interface) provider side packet interfaces ? 100 mbps mii fast ethernet or 1000 mbps gmii/tbi gigabit ethernet april 2005 ordering information zl50115gag 324 ball pbga trays, bake & dry pack zl50116gag 324 ball pbga trays, bake & dry pack zl50117gag 324 ball pbga trays, bake & dry pack zl50118gag 324 ball pbga trays, bake & dry pack zl50119gag 324 ball pbga trays, bake & dry pack ZL50120gag 324 ball pbga trays, bake & dry pack -40 c to +85 c zl50115/16/17/18/19/20 32, 64 and 128 channel cesop processors data sheet figure 1 - zl50115/16/17/18/19/20 high level overview on chip packet memory (jitter buffer compensation for 128 ms of packet delay variation) dual reference stratum 3 dpll host processor interface jtag 4 t1/e1, 1 j2/t3/e3 or 1 sts-1 ports h.110, h-mvip, st-bus backplanes 100 mbps mii fast ethernet 100 mbps mii fast ethernet or 1000 mbps gmii/tbi gigabit ethernet backplane clocks 32-bit motorola compatible dma for signaling packets multi-protocol packet processing engine pw, rtp, udp, ipv4, ipv6, mpls, ecid, vlan, user defined, others dual packet interface mac (mii, gmii, tbi) tdm interface (liu, framer, backplane) per port dco for clock recovery
zl50115/16/17/18/19/20 data sheet 2 zarlink semiconductor inc. system interfaces ? flexible 32 bit motorola host interface ? on-chip packet memory with jitter buffer compensation for over 128 ms of packet delay variation packet processing functions ? flexible, multi-protocol packet encapsulation includi ng ipv4, ipv6, rtp, mpls, l2tpv3, itu-t y.1413, ietf cesopsn, ietf satop and user programmable ? packet re-sequencing to allow lost packet detection and re-ordering ? four classes of service with programmable prio rity mechanisms (wfq and sp) using egress queues ? programmable classification of incoming packets at layers 2 through 5 ? wire speed processing of all packets regard less of classification providing low latency ? supports up to 128 separate cesop connections across the packet switched network applications ? circuit emulation services over packet networks ? leased line support over packet networks ? tdm over cable ? tdm over wifi (802.11x) ? tdm over wimax (802.16) ? fibre to the premises g/e-pon ? layer 2 vpn services ? customer-premise and provider edge routers and switches ? ethernet and ip based iads zl50115/16/17/18/19/20 data sheet 3 zarlink semiconductor inc. 1.0 changes summary the following table captures the changes from the january 2005 issue. the following table captures the changes from the november 2004 issue. page item change clarified data sheet to indi cate zl5011x supports clock recovery in both synchronous and asynchronous modes of operation. 84 figure 43 inverted polarity of cpu_dreq0 and cpu_dreq1 to conform with default mpc8260. polarity of cpu_dreq and cpu_sdack remains programmable through api. 84 figure 44 inverted polarity of cpu_dreq0 and cpu_dreq1 to conform with default mpc8260. polarity of cpu_dreq and cpu_sdack remains programmable through api. page item change 38 section 4.6.1 added 5 kohm pulldown recommendation to gpio signals. zl50115/16/17/18/19/20 data sheet 4 zarlink semiconductor inc. 2.0 device line up there are three products within the zl5011x family, with capacities as shown in table 1. product number tdm interface provider side packet interface customer side packet interface zl50115 1 t1 or 1 e1 stream or 1 mvip/st-bus stream at 2.048 mbps or 1 h.110/h-mvip/st-bus streams at 8.192 mbps (maximum of 32 ds0 or nx64 kbps channels) 100 mbps mii or 1000 mbps gmii/tbi none zl50116 2 t1 or 2 e1 streams or 2 mvip/st-bus streams at 2.048 mbps or 1 h.110/h-mvip/st-bus streams at 8.192 mbps (maximum of 64 ds0 or nx64 kbps channels) 100 mbps mii or 1000 mbps gmii/tbi none zl50117 4 t1 or 4 e1 streams or 1 j2, 1 t3, 1 e3 or 1 sts-1 stream or 4 mvip/st-bus streams at 2.048 mbps or 1 h.110/h-mvip/st-bus streams at 8.192 mbps 100 mbps mii or 1000 mbps gmii/tbi none zl50118 1 t1 or 1 e1 stream or 1 mvip/st-bus stream at 2.048 mbps or 1 h.110/h-mvip/st-bus streams at 8.192 mbps (maximum of 32 ds0 or nx64 kbps channels) 100 mbps mii or 1000 mbps gmii/tbi 100 mbps mii zl50119 2 t1 or 2 e1 streams or 2 mvip/st-bus streams at 2.048 mbps or 1 h.110/h-mvip/st-bus streams at 8.192 mbps (maximum of 64 ds0 or nx64 kbps channels) 100 mbps mii or 1000 mbps gmii/tbi 100 mbps mii ZL50120 4 t1 or 4 e1 streams or 1 j2, 1 t3, 1 e3 or 1 sts-1 stream or 4 mvip/st-bus streams at 2.048 mbps or 1 h.110/h-mvip/st-bus streams at 8.192 mbps 100 mbps mii or 1000 mbps gmii/tbi 100 mbps mii table 1 - capacity of devices in the zl50115/16/17/18/19/20 family zl50115/16/17/18/19/20 data sheet 5 zarlink semiconductor inc. 2.0 description the zl5011x family (zl50115, zl50116, zl50117, zl50118, zl50119, ZL50120) of cesop processors are highly functional tdm to packet bridging dev ices. the zl5011x provides both structured and unstructured circuit emulation services (cesop) for t1 and e1 streams across a packet network based on mpls, ip or ethernet. the zl50117/20 also supports unstructured j2, t3, e3 and sts-1. the circuit emulation features in the zl5011x family comply with the itu recommendation y.1413, as well as the implementation agreements for cesop from the metro et hernet forum (mef 8) and the mpls and frame relay alliance (mfa 8.0.0). the zl5011x also complies with the standards currently being developed within the ietf's pwe3 working group, listed below. ? structure-agnostic tdm over packet (satop) - draft-ietf-pwe3-satop ? structure-aware tdm circuit emulation serv ice over packet switched network (cesopsn) - draft-ietf-pwe3-cesopsn the zl50118/19/20 provides a customer side 100 mbps mii por t to aggregate data traffic with voice traffic to the provider side 1000 mbps gmii/tbi port, thereby elim inating the need for an exte rnal ethernet switch. the zl5011x incorporates a range of powerful clock recovery mechanisms for each tdm stream, allowing the frequency of the source clock to be fa ithfully generated at the destinatio n, enabling greater system performance and quality. timing is carried using rtp or similar prot ocols, and both adaptive and differential clock recovery schemes are included, allowing the customer to choose the correct scheme for the application. an externally supplied clock may also be used to driv e the tdm interface of the zl5011x. the zl5011x incur very low latency for the data flow, thereby increasing qos when carrying voice services across the packet switched network. voice, when carried using cesop, which typically has latencies of less than 10 ms, does not require expensive processing such as compression and echo cancellation. the zl5011x are cost effective device s aimed at the low density applications such as customer premise routers, iads, epon termination and broadband dlcs. for networ k systems, the zl5011x is fully compatible and interoperable with the zl50110/11/14 family. the zl5011x is capable of assembling user-defined packets of tdm traffic from the tdm interface and transmitting them out the packet interfaces using a variety of prot ocols. the zl5011x supports a range of different packet switched networks, including ethernet vlans, ip (both ve rsions 4 and 6) and mpls. the devices also supports four different classes of service on pa cket egress, allowing priority treatment of tdm-based traffic. this can be used to help minimize latency variation in the tdm data. packets received from the packet interfaces are pars ed to determine the egress des tination, and are appropriately queued to the tdm interface, they can also be forwarded to the host interface, or back toward the packet interface. packets queued to the tdm interface can be re-ordered based on sequence num ber, and lost packets filled in to maintain timing integrity. the zl5011x includes on-chip memory sufficient for all applications, thereby reducin g system costs, board area, power, and design complexity. a comprehensive evaluation system is available upon request from your local zarlink re presentative or distributor. this system includes the cesop processor, various tdm interfaces and a fully featured evaluation software gui that will run on a windows pc. zl50115/16/17/18/19/20 data sheet table of contents 6 zarlink semiconductor inc. 1.0 changes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.0 device line up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.0 physical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.0 external interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 tdm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.1 tdm stream connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.2 tdm signals common to zl50115/16/17/18/19/20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 pac interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3 packet interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.4 cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.5 system function interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.6 test facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.6.1 administration, control and test interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.6.2 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.7 miscellaneous inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.8 power and ground connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.9 internal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.10 no connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.11 device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.0 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1 leased line provision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2 remote concentrator unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3 fttp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4 wireless - wifi or wimax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.5 digital loop carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.6 integrated access device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.2 data and control flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3 tdm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.1 tdm interface block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.2 structured tdm port data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.3 tdm clock structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.3.1 synchronous tdm clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.3.2 asynchronous tdm clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.4 payload assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.4.1 structured payload operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4.1.1 payload order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.4.2 unstructured payload operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.5 protocol engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.6 packet transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.7 packet reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.8 tdm formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.9 ethernet traffic aggregation (zl50118/19/20 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.0 clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.1 differential clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.2 adaptive clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.0 system features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.1 latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.2 loopback modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 zl50115/16/17/18/19/20 data sheet table of contents 7 zarlink semiconductor inc. 8.3 host packet generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.4 loss of service (los) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.5 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.6 jtag interface and board level test features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.7 external component requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.8 miscellaneous features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.9 test modes operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.9.1.1 system normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.9.1.2 system tri-state mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.9.2 test mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.9.3 system normal mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.9.4 system tri-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.0 dpll specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1.1 locking mode (normal operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1.2 holdover mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.1.3 freerun mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.1.4 powerdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.2 reference monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.3 locking mode reference switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.4 locking range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.5 locking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.6 lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7 jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7.1 acceptance of input wander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7.2 intrinsic jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7.3 jitter tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7.4 jitter transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.8 maximum time interval error (mtie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.0 memory map and register definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.0 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.0 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.1 tdm interface timing - st-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.1.1 st-bus slave clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.1.2 st-bus master clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.2 tdm interface timing - h.110 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.3 tdm interface timing - h-mvip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.4 tdm liu interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.5 pac interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.6 packet interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.6.1 mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.6.2 mii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.6.3 gmii transmit timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.6.4 gmii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.6.5 tbi interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.6.6 management interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.7 cpu interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.8 system function port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.9 jtag interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.0 power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 zl50115/16/17/18/19/20 data sheet table of contents 8 zarlink semiconductor inc. 14.0 design and layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.1 high speed clock & data interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.1.1 gmac interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.1.2 tdm interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.1.3 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.2 cpu ta output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15.0 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 15.1 external standards/specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 15.2 zarlink standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 16.0 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 zl50115/16/17/18/19/20 data sheet list of figures 9 zarlink semiconductor inc. figure 1 - zl50115/16/17/18/19/20 high level overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - zl50115 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3 - zl50116 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4 - zl50117 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5 - zl50118 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6 - zl50119 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7 - ZL50120 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8 - leased line services over a circuit emulation link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 9 - remote concentrator unit using cesop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 10 - epon using cesop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 11 - wi-fi and wimax using cesop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 12 - digital loop carrier using cesop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 13 - integrated access device usin g cesop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 14 - zl50115/16/17/18/19/20 family oper ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 15 - zl50115/16/17/18/19/20 data and c ontrol flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 16 - synchronous tdm clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 17 - zl50115/16/17/18/19/20 packet form at - structured mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 18 - channel order for packet formation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 19 - zl50115/16/17/18/19/20 packet form at - unstructured mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 20 - differential clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 21 - adaptive clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 22 - powering up the zl5011x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 23 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 24 - jitter transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 25 - jitter transfer function - detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 26 - tdm st-bus slave mode timing at 8.192 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 27 - tdm st-bus slave mode timing at 2.048 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 28 - tdm bus master mode timing at 8.192 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 29 - tdm bus master mode timing at 2.048 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 30 - h.110 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 31 - tdm - h-mvip timing diagram for 16 mhz clock (8.192 mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 32 - tdm-liu structured transmission/reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 33 - mii transmit timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 34 - mii receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 35 - gmii transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 36 - gmii receive timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 37 - tbi transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 38 - tbi receive timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 39 - management interface timing for ethernet port - r ead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 40 - management interface timing for ethernet port - wr ite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 41 - cpu read - mpc8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 42 - cpu write - mpc8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 43 - cpu dma read - mpc8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 44 - cpu dma write - mpc8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 45 - jtag signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 46 - jtag clock and reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 47 - zl50115/16/17/18/19/20 power consum ption plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 48 - cpu_ta board circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 zl50115/16/17/18/19/20 data sheet list of tables 10 zarlink semiconductor inc. table 1 - capacity of devices in the zl50115/16/17/18/19/20 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2 - zl50115/16/17/18/19/20 ball signal assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3 - tdm interface stream pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 4 - tdm interface common pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5 - pac interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6 - packet interface signal mapping - mii to gmii/tbi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 7 - mii management interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8 - mii port 0 interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9 - mii port 1 interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10 - cpu interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11 - system function interface package ball definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 12 - administration/control interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 13 - jtag interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 14 - miscellaneous inputs package ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 15 - power and ground package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16 - internal connections package ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17 - miscellaneous inputs package ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18 - device id ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 19 - standard device flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 20 - tdm services offered by the zl50115/16/17/18/19/20 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 21 - some of the tdm port formats accepted by the zl50115/16/17/18/19/20 family . . . . . . . . . . . . . . . 50 table 22 - dma maximum bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 23 - test mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 24 - dpll input reference frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 25 - tdm st-bus master timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 26 - tdm h.110 timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 27 - tdm h-mvip timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 28 - tdm - liu structured transmission/reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 29 - pac timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 30 - mii transmit timing - 100 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 31 - mii receive timing - 100 mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 32 - gmii transmit timing - 1000 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 33 - gmii receive timing - 1000 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 34 - tbi timing - 1000 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 35 - mac management timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 36 - cpu timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 37 - system clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 38 - jtag interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 zl50115/16/17/18/19/20 data sheet 11 zarlink semiconductor inc. 3.0 physical specification the zl5011x will be packaged in a pbga device. features: ? body size: 23 mm x 23 mm (typ) ? ball count: 324 ? ball pitch: 1.00 mm (typ) ? ball matrix: 22 x 22 ? ball diameter: 0.60 mm (typ) ? total package thickness: 2.03 mm (typ) zl50115/16/17/18/19/20 data sheet 12 zarlink semiconductor inc. zl50115 package view from top side. note that ball a1 is non-chamfered corner. figure 2 - zl50115 package view and ball positions 12345678910111213141516171819202122 a vdd_io nc m0_txclk m0_rxd[7] m0_rxd[6] m0_rxd[4] m0_col m0_gtx_c lk m0_txen device_id [4] cpu_data[ 28] cpu_data[ 24] gnd cpu_data[ 23] gnd cpu_data[ 19] cpu_data[ 12] cpu_data[ 9] cpu_data[ 8] cpu_data[ 7] cpu_sdac k1 vdd_io b nc vdd_io gnd nc nc m0_crs m0_rxd[0] m0_rbc1 m0_rbc0 m0_txer gnd m0_txd[5] m0_txd[3] m0_txd[2] nc cpu_data[ 27] cpu_data[ 22] cpu_data[ 20] cpu_data[ 13] gnd vdd_io cpu_ta c nc gnd vdd_io nc nc nc m0_rxdv m0_rxd[3] m0_rxd[1] m0_rxclk m0_txd[7] m0_txd[4] m0_txd[0] vdd_io vdd_io cpu_data[ 31] nc cpu_data[ 29] cpu_data[ 26] vdd_io gnd cpu_dre q1 d nc nc nc vdd_io nc m0_rxer vdd_io m0_rxd[5] vdd_cor e m0_rxd[2] m0_refcl k m0_txd[6] m0_txd[1] vdd_cor e vdd_cor e vdd_io m0_activ e_led vdd_cor e vdd_io cpu_data[ 25] cpu_addr [23] cpu_data[ 6] e nc m0_gigabi t_led nc nc cpu_data[ 30] cpu_data[ 21] cpu_data[ 15] cpu_data[ 14] f nc nc device_id [1] vdd_cor e vdd_cor e cpu_data[ 18] cpu_data[ 17] cpu_data[ 16] g m_mdio device_id [0] m0_linku p_led vdd_io vdd_io cpu_ireq 1 cpu_data[ 11] cpu_data[ 0] h m_mdc gnd nc vdd_cor e cpu_data[ 10] cpu_data[ 1] cpu_data[ 4] ic j nc nc nc vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_data[ 5] cpu_data[ 3] cpu_ireq 0 k nc nc nc vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_data[ 2] ic cpu_dre q0 l gnd aux_clko aux_clki vdd_cor e gnd gnd gnd gnd gnd gnd cpu_clk gnd cpu_sdac k2 ic_vdd_io m nc nc nc vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_ts_a le cpu_we cpu_oe n nc nc nc vdd_cor e gnd gnd gnd gnd gnd gnd vdd_io cpu_add r[22] cpu_cs cpu_addr [19] p nc gnd vdd_io vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_add r[17] cpu_addr [18] cpu_addr [21] r nc nc tdm_clki[ 0] nc gnd cpu_add r[11] cpu_addr [13] cpu_addr [20] t nc nc tdm_frmi _ref vdd_io vdd_io vdd_io cpu_addr [14] cpu_addr [16] u tdm_sti[0]vdd_io gnd tdm_clki s vdd_cor e jtag_tms cpu_addr [15] cpu_addr [12] v tdm_sto[ 0] tdm_clko [0] tdm_clko _ref tdm_clki p device_id [3] jtag_tck cpu_addr [10] cpu_addr [9] w ic tdm_clki _ref tdm_frm o_ref vdd_io vdd_io vdd_cor e vdd_io vdd_io vdd_cor e pll_sec ic_gnd gnd system_c lk vdd_cor e gpio[9] vdd_io gpio[15] device_id [2] vdd_io jtag_tdo cpu_addr [4] cpu_addr [8] y ic gnd vdd_io ic ic vdd_cor e ic ic pll_pri ic ic_gnd ic gnd gnd gpio[8] gpio[14] test_mod e[1] jtag_trs t ic_gnd vdd_io gnd cpu_addr [7] aa ic vdd_io gnd vdd_io vdd_io ic gnd a1vdd_pl l1 ic ic system_d ebug system_r st gpio[1] gpio[2] gpio[7] gpio[12] test_mod e[0] jtag_tdi ic_gnd gnd vdd_io cpu_addr [6] ab vdd_io ic ic ic gnd ic ic ic gpio[0] gpio[3] gpio[4] gpio[5] gpio[6] gpio[10] gpio[11] gpio[13] test_mod e[2] ic_gnd cpu_add r[2] cpu_add r[3] cpu_addr [5] vdd_io zl50115/16/17/18/19/20 data sheet 13 zarlink semiconductor inc. zl50116 package view from top side. note that ball a1 is non-chamfered corner. figure 3 - zl50116 package view and ball positions 12345678910111213141516171819202122 a vdd_io nc m0_txclk m0_rxd[7] m0_rxd[6] m0_rxd[4] m0_col m0_gtx_c lk m0_txen device_id [4] cpu_data[ 28] cpu_data[ 24] gnd cpu_data[ 23] gnd cpu_data[ 19] cpu_data[ 12] cpu_data[ 9] cpu_data[ 8] cpu_data[ 7] cpu_sdac k1 vdd_io b nc vdd_io gnd nc nc m0_crs m0_rxd[0] m0_rbc1 m0_rbc0 m0_txer gnd m0_txd[5] m0_txd[3] m0_txd[2] nc cpu_data[ 27] cpu_data[ 22] cpu_data[ 20] cpu_data[ 13] gnd vdd_io cpu_ta c nc gnd vdd_io nc nc nc m0_rxdv m0_rxd[3] m0_rxd[1] m0_rxclk m0_txd[7] m0_txd[4] m0_txd[0] vdd_io vdd_io cpu_data[ 31] nc cpu_data[ 29] cpu_data[ 26] vdd_io gnd cpu_dre q1 d nc nc nc vdd_io nc m0_rxer vdd_io m0_rxd[5] vdd_cor e m0_rxd[2] m0_refcl k m0_txd[6] m0_txd[1] vdd_cor e vdd_cor e vdd_io m0_activ e_led vdd_cor e vdd_io cpu_data[ 25] cpu_addr [23] cpu_data[ 6] e nc m0_gigabi t_led nc nc cpu_data[ 30] cpu_data[ 21] cpu_data[ 15] cpu_data[ 14] f nc nc device_id [1] vdd_cor e vdd_cor e cpu_data[ 18] cpu_data[ 17] cpu_data[ 16] g m_mdio device_id [0] m0_linku p_led vdd_io vdd_io cpu_ireq 1 cpu_data[ 11] cpu_data[ 0] h m_mdc gnd nc vdd_cor e cpu_data[ 10] cpu_data[ 1] cpu_data[ 4] ic j nc nc nc vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_data[ 5] cpu_data[ 3] cpu_ireq 0 k nc nc nc vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_data[ 2] ic cpu_dre q0 l gnd aux_clko aux_clki vdd_cor e gnd gnd gnd gnd gnd gnd cpu_clk gnd cpu_sdac k2 ic_vdd_io m nc nc nc vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_ts_a le cpu_we cpu_oe n nc nc nc vdd_cor e gnd gnd gnd gnd gnd gnd vdd_io cpu_add r[22] cpu_cs cpu_addr [19] p nc gnd vdd_io vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_add r[17] cpu_addr [18] cpu_addr [21] r nc tdm_sti[1]tdm_clki[ 0] tdm_sto[ 1] gnd cpu_add r[11] cpu_addr [13] cpu_addr [20] t tdm_clki[ 1] tdm_clko [1] tdm_frmi _ref vdd_io vdd_io vdd_io cpu_addr [14] cpu_addr [16] u tdm_sti[0]vdd_io gnd tdm_clki s vdd_cor e jtag_tms cpu_addr [15] cpu_addr [12] v tdm_sto[ 0] tdm_clko [0] tdm_clko _ref tdm_clki p device_id [3] jtag_tck cpu_addr [10] cpu_addr [9] w ic tdm_clki _ref tdm_frm o_ref vdd_io vdd_io vdd_cor e vdd_io vdd_io vdd_cor e pll_sec ic_gnd gnd system_c lk vdd_cor e gpio[9] vdd_io gpio[15] device_id [2] vdd_io jtag_tdo cpu_addr [4] cpu_addr [8] y ic gnd vdd_io ic ic vdd_cor e ic ic pll_pri ic ic_gnd ic gnd gnd gpio[8] gpio[14] test_mod e[1] jtag_trs t ic_gnd vdd_io gnd cpu_addr [7] aa ic vdd_io gnd vdd_io vdd_io ic gnd a1vdd_pl l1 ic ic system_d ebug system_r st gpio[1] gpio[2] gpio[7] gpio[12] test_mod e[0] jtag_tdi ic_gnd gnd vdd_io cpu_addr [6] ab vdd_io ic ic ic gnd ic ic ic gpio[0] gpio[3] gpio[4] gpio[5] gpio[6] gpio[10] gpio[11] gpio[13] test_mod e[2] ic_gnd cpu_add r[2] cpu_add r[3] cpu_addr [5] vdd_io zl50115/16/17/18/19/20 data sheet 14 zarlink semiconductor inc. zl50117 package view from top side. note that ball a1 is non-chamfered corner. figure 4 - zl50117 package view and ball positions 12345678910111213141516171819202122 a vdd_io nc m0_txclk m0_rxd[7] m0_rxd[6] m0_rxd[4] m0_col m0_gtx_c lk m0_txen device_id [4] cpu_data[ 28] cpu_data[ 24] gnd cpu_data[ 23] gnd cpu_data[ 19] cpu_data[ 12] cpu_data[ 9] cpu_data[ 8] cpu_data[ 7] cpu_sdac k1 vdd_io b nc vdd_io gnd nc nc m0_crs m0_rxd[0] m0_rbc1 m0_rbc0 m0_txer gnd m0_txd[5] m0_txd[3] m0_txd[2] nc cpu_data[ 27] cpu_data[ 22] cpu_data[ 20] cpu_data[ 13] gnd vdd_io cpu_ta c nc gnd vdd_io nc nc nc m0_rxdv m0_rxd[3] m0_rxd[1] m0_rxclk m0_txd[7] m0_txd[4] m0_txd[0] vdd_io vdd_io cpu_data[ 31] nc cpu_data[ 29] cpu_data[ 26] vdd_io gnd cpu_dre q1 d nc nc nc vdd_io nc m0_rxer vdd_io m0_rxd[5] vdd_cor e m0_rxd[2] m0_refcl k m0_txd[6] m0_txd[1] vdd_cor e vdd_cor e vdd_io m0_activ e_led vdd_cor e vdd_io cpu_data[ 25] cpu_addr [23] cpu_data[ 6] e nc m0_gigabi t_led nc nc cpu_data[ 30] cpu_data[ 21] cpu_data[ 15] cpu_data[ 14] f nc nc device_id [1] vdd_cor e vdd_cor e cpu_data[ 18] cpu_data[ 17] cpu_data[ 16] g m_mdio device_id [0] m0_linku p_led vdd_io vdd_io cpu_ireq 1 cpu_data[ 11] cpu_data[ 0] h m_mdc gnd nc vdd_cor e cpu_data[ 10] cpu_data[ 1] cpu_data[ 4] ic j nc nc nc vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_data[ 5] cpu_data[ 3] cpu_ireq 0 k nc nc nc vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_data[ 2] ic cpu_dre q0 l gnd aux_clko aux_clki vdd_cor e gnd gnd gnd gnd gnd gnd cpu_clk gnd cpu_sdac k2 ic_vdd_io m tdm_clki[ 3] tdm_sto[ 3] tdm_sti[3]vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_ts_a le cpu_we cpu_oe n tdm_sto[ 2] tdm_clko [3] tdm_sti[2]vdd_cor e gnd gnd gnd gnd gnd gnd vdd_io cpu_add r[22] cpu_cs cpu_addr [19] p tdm_clki[ 2] gnd vdd_io vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_add r[17] cpu_addr [18] cpu_addr [21] r tdm_clko [2] tdm_sti[1]tdm_clki[ 0] tdm_sto[ 1] gnd cpu_add r[11] cpu_addr [13] cpu_addr [20] t tdm_clki[ 1] tdm_clko [1] tdm_frmi _ref vdd_io vdd_io vdd_io cpu_addr [14] cpu_addr [16] u tdm_sti[0]vdd_io gnd tdm_clki s vdd_cor e jtag_tms cpu_addr [15] cpu_addr [12] v tdm_sto[ 0] tdm_clko [0] tdm_clko _ref tdm_clki p device_id [3] jtag_tck cpu_addr [10] cpu_addr [9] w ic tdm_clki _ref tdm_frm o_ref vdd_io vdd_io vdd_cor e vdd_io vdd_io vdd_cor e pll_sec ic_gnd gnd system_c lk vdd_cor e gpio[9] vdd_io gpio[15] device_id [2] vdd_io jtag_tdo cpu_addr [4] cpu_addr [8] y ic gnd vdd_io ic ic vdd_cor e ic ic pll_pri ic ic_gnd ic gnd gnd gpio[8] gpio[14] test_mod e[1] jtag_trs t ic_gnd vdd_io gnd cpu_addr [7] aa ic vdd_io gnd vdd_io vdd_io ic gnd a1vdd_pl l1 ic ic system_d ebug system_r st gpio[1] gpio[2] gpio[7] gpio[12] test_mod e[0] jtag_tdi ic_gnd gnd vdd_io cpu_addr [6] ab vdd_io ic ic ic gnd ic ic ic gpio[0] gpio[3] gpio[4] gpio[5] gpio[6] gpio[10] gpio[11] gpio[13] test_mod e[2] ic_gnd cpu_add r[2] cpu_add r[3] cpu_addr [5] vdd_io zl50115/16/17/18/19/20 data sheet 15 zarlink semiconductor inc. zl50118 package view from top side. note that ball a1 is non-chamfered corner. figure 5 - zl50118 package view and ball positions 12345678910111213141516171819202122 a vdd_io m1_txen m0_txclk m0_rxd[7] m0_rxd[6] m0_rxd[4] m0_col m0_gtx_c lk m0_txen device_id [4] cpu_data[ 28] cpu_data[ 24] gnd cpu_data[ 23] gnd cpu_data[ 19] cpu_data[ 12] cpu_data[ 9] cpu_data[ 8] cpu_data[ 7] cpu_sdac k1 vdd_io b m1_txd[2] vdd_io gnd m1_txd[0] m1_txd[1] m0_crs m0_rxd[0] m0_rbc1 m0_rbc0 m0_txer gnd m0_txd[5] m0_txd[3] m0_txd[2] m1_activ e_led cpu_data[ 27] cpu_data[ 22] cpu_data[ 20] cpu_data[ 13] gnd vdd_io cpu_ta c m1_txd[3] gnd vdd_io m1_rxclk m1_col m1_txer m0_rxdv m0_rxd[3] m0_rxd[1] m0_rxclk m0_txd[7] m0_txd[4] m0_txd[0] vdd_io vdd_io cpu_data[ 31] m1_linku p_led cpu_data[ 29] cpu_data[ 26] vdd_io gnd cpu_dre q1 d m1_rxd[1] m1_rxd[0] m1_rxd[2] vdd_io m1_rxdv m0_rxer vdd_io m0_rxd[5] vdd_cor e m0_rxd[2] m0_refcl k m0_txd[6] m0_txd[1] vdd_cor e vdd_cor e vdd_io m0_activ e_led vdd_cor e vdd_io cpu_data[ 25] cpu_addr [23] cpu_data[ 6] e m1_rxd[3] m0_gigabi t_led m1_txclk m1_rxer cpu_data[ 30] cpu_data[ 21] cpu_data[ 15] cpu_data[ 14] f nc m1_crs device_id [1] vdd_cor e vdd_cor e cpu_data[ 18] cpu_data[ 17] cpu_data[ 16] g m_mdio device_id [0] m0_linku p_led vdd_io vdd_io cpu_ireq 1 cpu_data[ 11] cpu_data[ 0] h m_mdc gnd nc vdd_cor e cpu_data[ 10] cpu_data[ 1] cpu_data[ 4] ic j nc nc nc vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_data[ 5] cpu_data[ 3] cpu_ireq 0 k nc nc nc vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_data[ 2] ic cpu_dre q0 l gnd aux_clko aux_clki vdd_cor e gnd gnd gnd gnd gnd gnd cpu_clk gnd cpu_sdac k2 ic_vdd_io m nc nc nc vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_ts_a le cpu_we cpu_oe n nc nc nc vdd_cor e gnd gnd gnd gnd gnd gnd vdd_io cpu_add r[22] cpu_cs cpu_addr [19] p nc gnd vdd_io vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_add r[17] cpu_addr [18] cpu_addr [21] r nc nc tdm_clki[ 0] nc gnd cpu_add r[11] cpu_addr [13] cpu_addr [20] t nc nc tdm_frmi _ref vdd_io vdd_io vdd_io cpu_addr [14] cpu_addr [16] u tdm_sti[0] vdd_io gnd tdm_clki s vdd_cor e jtag_tms cpu_addr [15] cpu_addr [12] v tdm_sto[ 0] tdm_clko [0] tdm_clko _ref tdm_clki p device_id [3] jtag_tck cpu_addr [10] cpu_addr [9] w ic tdm_clki _ref tdm_frm o_ref vdd_io vdd_io vdd_cor e vdd_io vdd_io vdd_cor e pll_sec ic_gnd gnd system_c lk vdd_cor e gpio[9] vdd_io gpio[15] device_id [2] vdd_io jtag_tdo cpu_addr [4] cpu_addr [8] y ic gnd vdd_io ic ic vdd_cor e ic ic pll_pri ic ic_gnd ic gnd gnd gpio[8] gpio[14] test_mod e[1] jtag_trs t ic_gnd vdd_io gnd cpu_addr [7] aa ic vdd_io gnd vdd_io vdd_io ic gnd a1vdd_pl l1 ic ic system_d ebug system_r st gpio[1] gpio[2] gpio[7] gpio[12] test_mod e[0] jtag_tdi ic_gnd gnd vdd_io cpu_addr [6] ab vdd_io ic ic ic gnd ic ic ic gpio[0] gpio[3] gpio[4] gpio[5] gpio[6] gpio[10] gpio[11] gpio[13] test_mod e[2] ic_gnd cpu_add r[2] cpu_add r[3] cpu_addr [5] vdd_io zl50115/16/17/18/19/20 data sheet 16 zarlink semiconductor inc. zl50119 package view from top side. note that ball a1 is non-chamfered corner. figure 6 - zl50119 package view and ball positions 12345678910111213141516171819202122 a vdd_io m1_txen m0_txclk m0_rxd[7] m0_rxd[6] m0_rxd[4] m0_col m0_gtx_c lk m0_txen device_id [4] cpu_data[ 28] cpu_data[ 24] gnd cpu_data[ 23] gnd cpu_data[ 19] cpu_data[ 12] cpu_data[ 9] cpu_data[ 8] cpu_data[ 7] cpu_sdac k1 vdd_io b m1_txd[2] vdd_io gnd m1_txd[0] m1_txd[1] m0_crs m0_rxd[0] m0_rbc1 m0_rbc0 m0_txer gnd m0_txd[5] m0_txd[3] m0_txd[2] m1_activ e_led cpu_data[ 27] cpu_data[ 22] cpu_data[ 20] cpu_data[ 13] gnd vdd_io cpu_ta c m1_txd[3] gnd vdd_io m1_rxclk m1_col m1_txer m0_rxdv m0_rxd[3] m0_rxd[1] m0_rxclk m0_txd[7] m0_txd[4] m0_txd[0] vdd_io vdd_io cpu_data[ 31] m1_linku p_led cpu_data[ 29] cpu_data[ 26] vdd_io gnd cpu_dre q1 d m1_rxd[1] m1_rxd[0] m1_rxd[2] vdd_io m1_rxdv m0_rxer vdd_io m0_rxd[5] vdd_cor e m0_rxd[2] m0_refcl k m0_txd[6] m0_txd[1] vdd_cor e vdd_cor e vdd_io m0_activ e_led vdd_cor e vdd_io cpu_data[ 25] cpu_addr [23] cpu_data[ 6] e m1_rxd[3] m0_gigabi t_led m1_txclk m1_rxer cpu_data[ 30] cpu_data[ 21] cpu_data[ 15] cpu_data[ 14] f nc m1_crs device_id [1] vdd_cor e vdd_cor e cpu_data[ 18] cpu_data[ 17] cpu_data[ 16] g m_mdio device_id [0] m0_linku p_led vdd_io vdd_io cpu_ireq 1 cpu_data[ 11] cpu_data[ 0] h m_mdc gnd nc vdd_cor e cpu_data[ 10] cpu_data[ 1] cpu_data[ 4] ic j nc nc nc vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_data[ 5] cpu_data[ 3] cpu_ireq 0 k nc nc nc vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_data[ 2] ic cpu_dre q0 l gnd aux_clko aux_clki vdd_cor e gnd gnd gnd gnd gnd gnd cpu_clk gnd cpu_sdac k2 ic_vdd_io m nc nc nc vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_ts_a le cpu_we cpu_oe n nc nc nc vdd_cor e gnd gnd gnd gnd gnd gnd vdd_io cpu_add r[22] cpu_cs cpu_addr [19] p nc gnd vdd_io vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_add r[17] cpu_addr [18] cpu_addr [21] r nc tdm_sti[1] tdm_clki[ 0] tdm_sto[ 1] gnd cpu_add r[11] cpu_addr [13] cpu_addr [20] t tdm_clki[ 1] tdm_clko [1] tdm_frmi _ref vdd_io vdd_io vdd_io cpu_addr [14] cpu_addr [16] u tdm_sti[0] vdd_io gnd tdm_clki s vdd_cor e jtag_tms cpu_addr [15] cpu_addr [12] v tdm_sto[ 0] tdm_clko [0] tdm_clko _ref tdm_clki p device_id [3] jtag_tck cpu_addr [10] cpu_addr [9] w ic tdm_clki _ref tdm_frm o_ref vdd_io vdd_io vdd_cor e vdd_io vdd_io vdd_cor e pll_sec ic_gnd gnd system_c lk vdd_cor e gpio[9] vdd_io gpio[15] device_id [2] vdd_io jtag_tdo cpu_addr [4] cpu_addr [8] y ic gnd vdd_io ic ic vdd_cor e ic ic pll_pri ic ic_gnd ic gnd gnd gpio[8] gpio[14] test_mod e[1] jtag_trs t ic_gnd vdd_io gnd cpu_addr [7] aa ic vdd_io gnd vdd_io vdd_io ic gnd a1vdd_pl l1 ic ic system_d ebug system_r st gpio[1] gpio[2] gpio[7] gpio[12] test_mod e[0] jtag_tdi ic_gnd gnd vdd_io cpu_addr [6] ab vdd_io ic ic ic gnd ic ic ic gpio[0] gpio[3] gpio[4] gpio[5] gpio[6] gpio[10] gpio[11] gpio[13] test_mod e[2] ic_gnd cpu_add r[2] cpu_add r[3] cpu_addr [5] vdd_io zl50115/16/17/18/19/20 data sheet 17 zarlink semiconductor inc. ZL50120 package view from top side. note that ball a1 is non-chamfered corner. figure 7 - ZL50120 package view and ball positions 12345678910111213141516171819202122 a vdd_io m1_txen m0_txclk m0_rxd[7] m0_rxd[6] m0_rxd[4] m0_col m0_gtx_c lk m0_txen device_id [4] cpu_data[ 28] cpu_data[ 24] gnd cpu_data[ 23] gnd cpu_data[ 19] cpu_data[ 12] cpu_data[ 9] cpu_data[ 8] cpu_data[ 7] cpu_sdac k1 vdd_io b m1_txd[2] vdd_io gnd m1_txd[0] m1_txd[1] m0_crs m0_rxd[0] m0_rbc1 m0_rbc0 m0_txer gnd m0_txd[5] m0_txd[3] m0_txd[2] m1_activ e_led cpu_data[ 27] cpu_data[ 22] cpu_data[ 20] cpu_data[ 13] gnd vdd_io cpu_ta c m1_txd[3] gnd vdd_io m1_rxclk m1_col m1_txer m0_rxdv m0_rxd[3] m0_rxd[1] m0_rxclk m0_txd[7] m0_txd[4] m0_txd[0] vdd_io vdd_io cpu_data[ 31] m1_linku p_led cpu_data[ 29] cpu_data[ 26] vdd_io gnd cpu_dre q1 d m1_rxd[1] m1_rxd[0] m1_rxd[2] vdd_io m1_rxdv m0_rxer vdd_io m0_rxd[5] vdd_cor e m0_rxd[2] m0_refcl k m0_txd[6] m0_txd[1] vdd_cor e vdd_cor e vdd_io m0_activ e_led vdd_cor e vdd_io cpu_data[ 25] cpu_addr [23] cpu_data[ 6] e m1_rxd[3] m0_gigabi t_led m1_txclk m1_rxer cpu_data[ 30] cpu_data[ 21] cpu_data[ 15] cpu_data[ 14] f nc m1_crs device_id [1] vdd_cor e vdd_cor e cpu_data[ 18] cpu_data[ 17] cpu_data[ 16] g m_mdio device_id [0] m0_linku p_led vdd_io vdd_io cpu_ireq 1 cpu_data[ 11] cpu_data[ 0] h m_mdc gnd nc vdd_cor e cpu_data[ 10] cpu_data[ 1] cpu_data[ 4] ic j nc nc nc vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_data[ 5] cpu_data[ 3] cpu_ireq 0 k nc nc nc vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_data[ 2] ic cpu_dre q0 l gnd aux_clko aux_clki vdd_cor e gnd gnd gnd gnd gnd gnd cpu_clk gnd cpu_sdac k2 ic_vdd_io m tdm_clki[ 3] tdm_sto[ 3] tdm_sti[3] vdd_io gnd gnd gnd gnd gnd gnd gnd cpu_ts_a le cpu_we cpu_oe n tdm_sto[ 2] tdm_clko [3] tdm_sti[2] vdd_cor e gnd gnd gnd gnd gnd gnd vdd_io cpu_add r[22] cpu_cs cpu_addr [19] p tdm_clki[ 2] gnd vdd_io vdd_cor e gnd gnd gnd gnd gnd gnd vdd_cor e cpu_add r[17] cpu_addr [18] cpu_addr [21] r tdm_clko [2] tdm_sti[1] tdm_clki[ 0] tdm_sto[ 1] gnd cpu_add r[11] cpu_addr [13] cpu_addr [20] t tdm_clki[ 1] tdm_clko [1] tdm_frmi _ref vdd_io vdd_io vdd_io cpu_addr [14] cpu_addr [16] u tdm_sti[0] vdd_io gnd tdm_clki s vdd_cor e jtag_tms cpu_addr [15] cpu_addr [12] v tdm_sto[ 0] tdm_clko [0] tdm_clko _ref tdm_clki p device_id [3] jtag_tck cpu_addr [10] cpu_addr [9] w ic tdm_clki _ref tdm_frm o_ref vdd_io vdd_io vdd_cor e vdd_io vdd_io vdd_cor e pll_sec ic_gnd gnd system_c lk vdd_cor e gpio[9] vdd_io gpio[15] device_id [2] vdd_io jtag_tdo cpu_addr [4] cpu_addr [8] y ic gnd vdd_io ic ic vdd_cor e ic ic pll_pri ic ic_gnd ic gnd gnd gpio[8] gpio[14] test_mod e[1] jtag_trs t ic_gnd vdd_io gnd cpu_addr [7] aa ic vdd_io gnd vdd_io vdd_io ic gnd a1vdd_pl l1 ic ic system_d ebug system_r st gpio[1] gpio[2] gpio[7] gpio[12] test_mod e[0] jtag_tdi ic_gnd gnd vdd_io cpu_addr [6] ab vdd_io ic ic ic gnd ic ic ic gpio[0] gpio[3] gpio[4] gpio[5] gpio[6] gpio[10] gpio[11] gpio[13] test_mod e[2] ic_gnd cpu_add r[2] cpu_add r[3] cpu_addr [5] vdd_io zl50115/16/17/18/19/20 data sheet 18 zarlink semiconductor inc. ball # zl50115 signal name zl50116 signal name zl50117 signal name zl50118 signal name zl50119 signal name ZL50120 signal name variant a1 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all a10 device_id[4] device_id[4] device_id[4] device_id[4] device_id[4] device_id[4] all a11 cpu_data[28] cpu_data[28] cpu_data[28] cpu_data[28] cpu_data[28] cpu_data[28] all a12 cpu_data[24] cpu_data[24] cpu_data[24] cpu_data[24] cpu_data[24] cpu_data[24] all a13 gnd gnd gnd gnd gnd gnd all a14 cpu_data[23] cpu_data[23] cpu_data[23] cpu_data[23] cpu_data[23] cpu_data[23] all a15 gnd gnd gnd gnd gnd gnd all a16 cpu_data[19] cpu_data[19] cpu_data[19] cpu_data[19] cpu_data[19] cpu_data[19] all a17 cpu_data[12] cpu_data[12] cpu_data[12] cpu_data[12] cpu_data[12] cpu_data[12] all a18 cpu_data[9] cpu_data[9] cpu_data[9] cpu_data[9] cpu_data[9] cpu_data[9] all a19 cpu_data[8] cpu_data[8] cpu_data[8] cpu_data[8] cpu_data[8] cpu_data[8] all a20 cpu_data[7] cpu_data[7] cpu_data[7] cpu_data[7] cpu_data[7] cpu_data[7] all a21 cpu_sdack1 cpu_sdack1 cpu_sdack1 cpu_sdack1 cpu_sdack1 cpu_sdack1 all a22 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all a2 nc nc nc m1_txen m1_txen m1_txen zl50118/19/20 a3 m0_txclk m0_txclk m0_txclk m0_txclk m0_txclk m0_txclk all a4 m0_rxd[7] m0_rxd[7] m0_rxd[7] m0_rxd[7] m0_rxd[7] m0_rxd[7] all a5 m0_rxd[6] m0_rxd[6] m0_rxd[6] m0_rxd[6] m0_rxd[6] m0_rxd[6] all a6 m0_rxd[4] m0_rxd[4] m0_rxd[4] m0_rxd[4] m0_rxd[4] m0_rxd[4] all a7 m0_col m0_col m0_col m 0_col m0_col m0_col all a8 m0_gtx_clk m0_gtx_clk m0_gtx_clk m0_gtx_clk m0_gtx_clk m0_gtx_clk all a9 m0_txen m0_txen m0_txen m0_txen m0_txen m0_txen all b1 nc nc nc m1_txd[2] m1_txd[2] m1_txd[2] zl50118/19/20 b10 m0_txer m0_txer m0_txer m0_txer m0_txer m0_txer all b11 gnd gnd gnd gnd gnd gnd all b12 m0_txd[5] m0_txd[5] m0_txd[5] m0_txd[5] m0_txd[5] m0_txd[5] all b13 m0_txd[3] m0_txd[3] m0_txd[3] m0_txd[3] m0_txd[3] m0_txd[3] all b14 m0_txd[2] m0_txd[2] m0_txd[2] m0_txd[2] m0_txd[2] m0_txd[2] all b15 nc nc nc m1_active_led m1_active_led m1_active_led zl50118/19/20 b16 cpu_data[27] cpu_data[27] cpu_data[27] cpu_data[27] cpu_data[27] cpu_data[27] all b17 cpu_data[22] cpu_data[22] cpu_data[22] cpu_data[22] cpu_data[22] cpu_data[22] all b18 cpu_data[20] cpu_data[20] cpu_data[20] cpu_data[20] cpu_data[20] cpu_data[20] all b19 cpu_data[13] cpu_data[13] cpu_data[13] cpu_data[13] cpu_data[13] cpu_data[13] all b20 gnd gnd gnd gnd gnd gnd all b21 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all b22 cpu_ta cpu_ta cpu_ta cpu_ta cpu_ta cpu_ta all b2 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all b3 gnd gnd gnd gnd gnd gnd all b4 nc nc nc m1_txd[0] m1_txd[0] m1_txd[0] zl50118/19/20 b5 nc nc nc m1_txd[1] m1_txd[1] m1_txd[1] zl50118/19/20 b6 m0_crs m0_crs m0_crs m0_crs m0_crs m0_crs all b7 m0_rxd[0] m0_rxd[0] m0_rxd[0] m0_rxd[0] m0_rxd[0] m0_rxd[0] all b8 m0_rbc1 m0_rbc1 m0_rbc1 m0_rbc1 m0_rbc1 m0_rbc1 all table 2 - zl50115/16/17/18/19/20 ball signal assignment zl50115/16/17/18/19/20 data sheet 19 zarlink semiconductor inc. b9 m0_rbc0 m0_rbc0 m0_rbc0 m0_rbc0 m0_rbc0 m0_rbc0 all c1 nc nc nc m1_txd[3] m1_txd[3] m1_txd[3] zl50118/19/20 c10 m0_rxclk m0_rxclk m0_rxclk m0_rxclk m0_rxclk m0_rxclk all c11 m0_txd[7] m0_txd[7] m0_txd[7] m0_txd[7] m0_txd[7] m0_txd[7] all c12 m0_txd[4] m0_txd[4] m0_txd[4] m0_txd[4] m0_txd[4] m0_txd[4] all c13 m0_txd[0] m0_txd[0] m0_txd[0] m0_txd[0] m0_txd[0] m0_txd[0] all c14 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all c15 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all c16 cpu_data[31] cpu_data[31] cpu_data[31] cpu_data[31] cpu_data[31] cpu_data[31] all c17 nc nc nc m1_linkup_led m1_linkup_led m1_linkup_led zl50118/19/20 c18 cpu_data[29] cpu_data[29] cpu_data[29] cpu_data[29] cpu_data[29] cpu_data[29] all c19 cpu_data[26] cpu_data[26] cpu_data[26] cpu_data[26] cpu_data[26] cpu_data[26] all c20 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all c21 gnd gnd gnd gnd gnd gnd all c22 cpu_dreq1 cpu_dreq1 cpu_dreq1 cpu_dreq1 cpu_dreq1 cpu_dreq1 all c2 gnd gnd gnd gnd gnd gnd all c3 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all c4 nc nc nc m1_rxclk m1_rxclk m1_rxclk zl50118/19/20 c5 nc nc nc m1_col m1_col m1_col zl50118/19/20 c6 nc nc nc m1_txer m1_txer m1_txer zl50118/19/20 c7 m0_rxdv m0_rxdv m0_rxdv m0_rxdv m0_rxdv m0_rxdv all c8 m0_rxd[3] m0_rxd[3] m0_rxd[3] m0_rxd[3] m0_rxd[3] m0_rxd[3] all c9 m0_rxd[1] m0_rxd[1] m0_rxd[1] m0_rxd[1] m0_rxd[1] m0_rxd[1] all d1 nc nc nc m1_rxd[1] m1_rxd[1] m1_rxd[1] zl50118/19/20 d10 m0_rxd[2] m0_rxd[2] m0_rxd[2] m0_rxd[2] m0_rxd[2] m0_rxd[2] all d11 m0_refclk m0_refclk m0_refclk m0_refclk m0_refclk m0_refclk all d12 m0_txd[6] m0_txd[6] m0_txd[6] m0_txd[6] m0_txd[6] m0_txd[6] all d13 m0_txd[1] m0_txd[1] m0_txd[1] m0_txd[1] m0_txd[1] m0_txd[1] all d14 vdd_core vdd_core vdd_core vdd_core vdd_core vdd_core all d15 vdd_core vdd_core vdd_core vdd_core vdd_core vdd_core all d16 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all d17 m0_active_led m0_active_led m0_active_led m0_active_led m0_active_led m0_active_led all d18 vdd_core vdd_core vdd_core vdd_core vdd_core vdd_core all d19 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all d20 cpu_data[25] cpu_data[25] cpu_data[25] cpu_data[25] cpu_data[25] cpu_data[25] all d21 cpu_addr[23] cpu_addr[23] cpu_addr[23] c pu_addr[23] cpu_addr[23] cpu_addr[23] all d22 cpu_data[6] cpu_data[6] cpu_data[6] cpu_data[6] cpu_data[6] cpu_data[6] all d2 nc nc nc m1_rxd[0] m1_rxd[0] m1_rxd[0] zl50118/19/20 d3 nc nc nc m1_rxd[2] m1_rxd[2] m1_rxd[2] zl50118/19/20 d4 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all d5 nc nc nc m1_rxdv m1_rxdv m1_rxdv zl50118/19/20 d6 m0_rxer m0_rxer m0_rxer m0_rxer m0_rxer m0_rxer all d7 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all ball # zl50115 signal name zl50116 signal name zl50117 signal name zl50118 signal name zl50119 signal name ZL50120 signal name variant table 2 - zl50115/16/17/18/19/20 ball signal assignment (continued) zl50115/16/17/18/19/20 data sheet 20 zarlink semiconductor inc. d8 m0_rxd[5] m0_rxd[5] m0_rxd[5] m0_rxd[5] m0_rxd[5] m0_rxd[5] all d9 vdd_core vdd_core vdd_core v dd_core vdd_core vdd_core all e1 nc nc nc m1_rxd[3] m1_rxd[3] m1_rxd[3] zl50118/19/20 e19 cpu_data[30] cpu_data[30] cpu_data[30] cpu_data[30] cpu_data[30] cpu_data[30] all e20 cpu_data[21] cpu_data[21] cpu_data[21] cpu_data[21] cpu_data[21] cpu_data[21] all e21 cpu_data[15] cpu_data[15] cpu_data[15] cpu_data[15] cpu_data[15] cpu_data[15] all e22 cpu_data[14] cpu_data[14] cpu_data[14] cpu_data[14] cpu_data[14] cpu_data[14] all e2 m0_gigabit_led m0_gigabit_led m0_gigabit_led m0_gigabit_led m0_gigabit_led m0_gigabit_led all e3 nc nc nc m1_txclk m1_txclk m1_txclk zl50118/19/20 e4 nc nc nc m1_rxer m1_rxer m1_rxer zl50118/19/20 f1 nc nc nc nc nc nc all f19 vdd_core vdd_core vdd_core vdd_core vdd_core vdd_core all f20 cpu_data[18] cpu_data[18] cpu_data[18] cpu_data[18] cpu_data[18] cpu_data[18] all f21 cpu_data[17] cpu_data[17] cpu_data[17] cpu_data[17] cpu_data[17] cpu_data[17] all f22 cpu_data[16] cpu_data[16] cpu_data[16] cpu_data[16] cpu_data[16] cpu_data[16] all f2 nc nc nc m1_crs m1_crs m1_crs zl50118/19/20 f3 device_id[1] device_id[1] device_id[1] d evice_id[1] device_id[ 1] device_id[1] all f4 vdd_core vdd_core vdd_core v dd_core vdd_core vdd_core all g1 m_mdio m_mdio m_mdio m_mdio m_mdio m_mdio all g19 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all g20 cpu_ireq1 cpu_ireq1 cpu_ireq1 cpu_ireq1 cpu_ireq1 cpu_ireq1 all g21 cpu_data[11] cpu_data[11] cpu_data[11] cpu_data[11] cpu_data[11] cpu_data[11] all g22 cpu_data[0] cpu_data[0] cpu_data[0] cpu_data[0] cpu_data[0] cpu_data[0] all g2 device_id[0] device_id[0] device_id[0] d evice_id[0] device_id[ 0] device_id[0] all g3 m0_linkup_led m0_linkup_led m0_linkup_led m0_linkup_led m0_linkup_led m0_linkup_led all g4 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all h1 m_mdc m_mdc m_mdc m_mdc m_mdc m_mdc all h19 cpu_data[10] cpu_data[10] cpu_data[10] cpu_data[10] cpu_data[10] cpu_data[10] all h20 cpu_data[1] cpu_data[1] cpu_data[1] cpu_data[1] cpu_data[1] cpu_data[1] all h21 cpu_data[4] cpu_data[4] cpu_data[4] cpu_data[4] cpu_data[4] cpu_data[4] all h22icicicic icicall h2 gnd gnd gnd gnd gnd gnd all h3 nc nc nc nc nc nc all h4 vdd_core vdd_core vdd_core v dd_core vdd_core vdd_core all j1 nc nc nc nc nc nc all j10 gnd gnd gnd gnd gnd gnd all j11 gnd gnd gnd gnd gnd gnd all j12 gnd gnd gnd gnd gnd gnd all j13 gnd gnd gnd gnd gnd gnd all j14 gnd gnd gnd gnd gnd gnd all j19 vdd_core vdd_core vdd_core vdd_core vdd_core vdd_core all j20 cpu_data[5] cpu_data[5] cpu_data[5] cpu_data[5] cpu_data[5] cpu_data[5] all j21 cpu_data[3] cpu_data[3] cpu_data[3] cpu_data[3] cpu_data[3] cpu_data[3] all ball # zl50115 signal name zl50116 signal name zl50117 signal name zl50118 signal name zl50119 signal name ZL50120 signal name variant table 2 - zl50115/16/17/18/19/20 ball signal assignment (continued) zl50115/16/17/18/19/20 data sheet 21 zarlink semiconductor inc. j22 cpu_ireq0 cpu_ireq0 cpu_ireq0 cpu_ireq0 cpu_ireq0 cpu_ireq0 all j2 nc nc nc nc nc nc all j3 nc nc nc nc nc nc all j4 vdd_core vdd_core vdd_core v dd_core vdd_core vdd_core all j9 gnd gnd gnd gnd gnd gnd all k1 nc nc nc nc nc nc all k10 gnd gnd gnd gnd gnd gnd all k11 gnd gnd gnd gnd gnd gnd all k12 gnd gnd gnd gnd gnd gnd all k13 gnd gnd gnd gnd gnd gnd all k14 gnd gnd gnd gnd gnd gnd all k19 gnd gnd gnd gnd gnd gnd all k20 cpu_data[2] cpu_data[2] cpu_data[2] cpu_data[2] cpu_data[2] cpu_data[2] all k21icicicic icicall k22 cpu_dreq0 cpu_dreq0 cpu_dreq0 cpu_dreq0 cpu_dreq0 cpu_dreq0 all k2 nc nc nc nc nc nc all k3 nc nc nc nc nc nc all k4 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all k9 gnd gnd gnd gnd gnd gnd all l1 gnd gnd gnd gnd gnd gnd all l10 gnd gnd gnd gnd gnd gnd all l11 gnd gnd gnd gnd gnd gnd all l12 gnd gnd gnd gnd gnd gnd all l13 gnd gnd gnd gnd gnd gnd all l14 gnd gnd gnd gnd gnd gnd all l19 cpu_clk cpu_clk cpu_clk cpu_clk cpu_clk cpu_clk all l20 gnd gnd gnd gnd gnd gnd all l21 cpu_sdack2 cpu_sdack2 cpu_sdack2 cpu_sdack2 cpu_sdack2 cpu_sdack2 all l22 ic_vdd_io ic_vdd_io ic_vdd_io ic_vdd_io ic_vdd_io ic_vdd_io all l2 aux_clko aux_clko aux_clko aux_clko aux_clko aux_clko all l3 aux_clki aux_clki aux_clki aux_clki aux_clki aux_clki all l4 vdd_core vdd_core vdd_core v dd_core vdd_core vdd_core all l9 gnd gnd gnd gnd gnd gnd all m1 nc nc tdm_clki[3] nc nc tdm_clki[3] zl50117/20 m10 gnd gnd gnd gnd gnd gnd all m11 gnd gnd gnd gnd gnd gnd all m12 gnd gnd gnd gnd gnd gnd all m13 gnd gnd gnd gnd gnd gnd all m14 gnd gnd gnd gnd gnd gnd all m19 gnd gnd gnd gnd gnd gnd all m20 cpu_ts_ale cpu_ts_ale cpu_ts_ale cpu_ts_ale cpu_ts_ale cpu_ts_ale all m21 cpu_we cpu_we cpu_we cpu_we cpu_we cpu_we all m22 cpu_oe cpu_oe cpu_oe cpu_oe cpu_oe cpu_oe all ball # zl50115 signal name zl50116 signal name zl50117 signal name zl50118 signal name zl50119 signal name ZL50120 signal name variant table 2 - zl50115/16/17/18/19/20 ball signal assignment (continued) zl50115/16/17/18/19/20 data sheet 22 zarlink semiconductor inc. m2 nc nc tdm_sto[3] nc nc tdm_sto[3] zl50117/20 m3 nc nc tdm_sti[3] nc nc tdm_sti[3] zl50117/20 m4 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all m9 gnd gnd gnd gnd gnd gnd all n1 nc nc tdm_sto[2] nc nc tdm_sto[2] zl50117/20 n10 gnd gnd gnd gnd gnd gnd all n11 gnd gnd gnd gnd gnd gnd all n12 gnd gnd gnd gnd gnd gnd all n13 gnd gnd gnd gnd gnd gnd all n14 gnd gnd gnd gnd gnd gnd all n19 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all n20 cpu_addr[22] cpu_addr[22] cpu_addr[22] c pu_addr[22] cpu_addr[22] cpu_addr[22] all n21 cpu_cs cpu_cs cpu_cs cpu_cs cpu_cs cpu_cs all n22 cpu_addr[19] cpu_addr[19] cpu_addr[19] c pu_addr[19] cpu_addr[19] cpu_addr[19] all n2 nc nc tdm_clko[3] nc nc tdm_clko[3] zl50117/20 n3 nc nc tdm_sti[2] nc nc tdm_sti[2] zl50117/20 n4 vdd_core vdd_core vdd_core v dd_core vdd_core vdd_core all n9 gnd gnd gnd gnd gnd gnd all p1 nc nc tdm_clki[2] nc nc tdm_clki[2] zl50117/20 p10 gnd gnd gnd gnd gnd gnd all p11 gnd gnd gnd gnd gnd gnd all p12 gnd gnd gnd gnd gnd gnd all p13 gnd gnd gnd gnd gnd gnd all p14 gnd gnd gnd gnd gnd gnd all p19 vdd_core vdd_core vdd_core vdd_core vdd_core vdd_core all p20 cpu_addr[17] cpu_addr[17] cpu_addr[17] c pu_addr[17] cpu_addr[17] cpu_addr[17] all p21 cpu_addr[18] cpu_addr[18] cpu_addr[18] c pu_addr[18] cpu_addr[18] cpu_addr[18] all p22 cpu_addr[21] cpu_addr[21] cpu_addr[21] c pu_addr[21] cpu_addr[21] cpu_addr[21] all p2 gnd gnd gnd gnd gnd gnd all p3 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all p4 vdd_core vdd_core vdd_core v dd_core vdd_core vdd_core all p9 gnd gnd gnd gnd gnd gnd all r1 nc nc tdm_clko[2] nc nc tdm_clko[2] zl50117/20 r19 gnd gnd gnd gnd gnd gnd all r20 cpu_addr[11] cpu_addr[11] cpu_addr[11] cpu_addr[11] cpu_addr[11] cpu_addr[11] all r21 cpu_addr[13] cpu_addr[13] cpu_addr[13] c pu_addr[13] cpu_addr[13] cpu_addr[13] all r22 cpu_addr[20] cpu_addr[20] cpu_addr[20] c pu_addr[20] cpu_addr[20] cpu_addr[20] all r2 nc tdm_sti[1] tdm_sti[1] nc tdm_sti[1] tdm_sti[1] zl50116/17/19/20 r3 tdm_clki[0] tdm_clki[0] tdm_clki[0] tdm_clki[0] tdm_clki[0] tdm_clki[0] all r4 nc tdm_sto[1] tdm_sto[1] nc tdm_sto[1] tdm_sto[1] zl50116/17/19/20 t1 nc tdm_clki[1] tdm_clki[1] nc tdm_clki[1] tdm_clki[1] zl50116/17/19/20 t19 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all t20 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all ball # zl50115 signal name zl50116 signal name zl50117 signal name zl50118 signal name zl50119 signal name ZL50120 signal name variant table 2 - zl50115/16/17/18/19/20 ball signal assignment (continued) zl50115/16/17/18/19/20 data sheet 23 zarlink semiconductor inc. t21 cpu_addr[14] cpu_addr[14] cpu_addr[14] c pu_addr[14] cpu_addr[14] cpu_addr[14] all t22 cpu_addr[16] cpu_addr[16] cpu_addr[16] c pu_addr[16] cpu_addr[16] cpu_addr[16] all t2 nc tdm_clko[1] tdm_clko[1] nc tdm_clko[1] tdm_clko[1] zl50116/17/19/20 t3 tdm_frmi_ref tdm_frmi_ref tdm_frmi_ref tdm_frmi_ref tdm_frmi_ref tdm_frmi_ref all t4 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all u1 tdm_sti[0] tdm_sti[0] tdm_sti[0] tdm_sti[0] tdm_sti[0] tdm_sti[0] all u19 vdd_core vdd_core vdd_core vdd_core vdd_core vdd_core all u20 jtag_tms jtag_tms jtag_tms jtag_tms jtag_tms jtag_tms all u21 cpu_addr[15] cpu_addr[15] cpu_addr[15] c pu_addr[15] cpu_addr[15] cpu_addr[15] all u22 cpu_addr[12] cpu_addr[12] cpu_addr[12] c pu_addr[12] cpu_addr[12] cpu_addr[12] all u2 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all u3 gnd gnd gnd gnd gnd gnd all u4 tdm_clkis tdm_clkis tdm_clkis tdm_clkis tdm_clkis tdm_clkis all v1 tdm_sto[0] tdm_sto[0] tdm_sto[0] tdm_sto[0] tdm_sto[0] tdm_sto[0] all v19 device_id[3] device_id[3] device_id[3] device_id[3] device_id[3] device_id[3] all v20 jtag_tck jtag_tck jtag_tck jtag_tck jtag_tck jtag_tck all v21 cpu_addr[10] cpu_addr[10] cpu_addr[10] c pu_addr[10] cpu_addr[10] cpu_addr[10] all v22 cpu_addr[9] cpu_addr[9] cpu_addr[9] cpu_addr[9] cpu_addr[9] cpu_addr[9] all v2 tdm_clko[0] tdm_clko[0] tdm_clko[0] tdm_clko[0] tdm_clko[0] tdm_clko[0] all v3 tdm_clko_ref tdm_clko_ref tdm_clko_ref tdm_clko_ref tdm_clko_ref tdm_clko_ref all v4 tdm_clkip tdm_clkip tdm_clkip tdm_clkip tdm_clkip tdm_clkip all w1 ic ic ic ic ic ic all w10 pll_sec pll_sec pll_sec pll_sec pll_sec pll_sec all w11 ic_gnd ic_gnd ic_gnd ic_gnd ic_gnd ic_gnd all w12 gnd gnd gnd gnd gnd gnd all w13 system_clk system_clk system_clk system_clk system_clk system_clk all w14 vdd_core vdd_core vdd_core vdd_core vdd_core vdd_core all w15 gpio[9] gpio[9] gpio[9] gpio[9] gpio[9] gpio[9] all w16 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all w17 gpio[15] gpio[15] gpio[15] gpio[15] gpio[15] gpio[15] all w18 device_id[2] device_id[2] device_id[2] device_id[2] device_id[2] device_id[2] all w19 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all w20 jtag_tdo jtag_tdo jtag_tdo jtag_tdo jtag_tdo jtag_tdo all w21 cpu_addr[4] cpu_addr[4] cpu_addr[4] cpu_addr[4] cpu_addr[4] cpu_addr[4] all w22 cpu_addr[8] cpu_addr[8] cpu_addr[8] cpu_addr[8] cpu_addr[8] cpu_addr[8] all w2 tdm_clki_ref tdm_clki_ref tdm_clki_ref tdm_clki_ref tdm_clki_ref tdm_clki_ref all w3 tdm_frmo_ref tdm_frmo_ref tdm_frmo_ref tdm_frmo_ref tdm_frmo_ref tdm_frmo_ref all w4 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all w5 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all w6 vdd_core vdd_core vdd_core v dd_core vdd_core vdd_core all w7 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all w8 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all w9 vdd_core vdd_core vdd_core v dd_core vdd_core vdd_core all ball # zl50115 signal name zl50116 signal name zl50117 signal name zl50118 signal name zl50119 signal name ZL50120 signal name variant table 2 - zl50115/16/17/18/19/20 ball signal assignment (continued) zl50115/16/17/18/19/20 data sheet 24 zarlink semiconductor inc. y1 ic ic ic ic ic ic all y10icicicic icicall y11 ic_gnd ic_gnd ic_gnd ic_gnd ic_gnd ic_gnd all y12icicicic icicall y13 gnd gnd gnd gnd gnd gnd all y14 gnd gnd gnd gnd gnd gnd all y15 gpio[8] gpio[8] gpio[8] gpio[8] gpio[8] gpio[8] all y16 gpio[14] gpio[14] gpio[14] gpio[14] gpio[14] gpio[14] all y17 test_mode[1] test_mode[1] test_mode[1] test_mode[1] test_mode[1] test_mode[1] all y18 jtag_trst jtag_trst jtag_trst jtag_trst jtag_trst jtag_trst all y19 ic_gnd ic_gnd ic_gnd ic_gnd ic_gnd ic_gnd all y20 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all y21 gnd gnd gnd gnd gnd gnd all y22 cpu_addr[7] cpu_addr[7] cpu_addr[7] cpu_addr[7] cpu_addr[7] cpu_addr[7] all y2 gnd gnd gnd gnd gnd gnd all y3 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all y4 ic ic ic ic ic ic all y5 ic ic ic ic ic ic all y6 vdd_core vdd_core vdd_core v dd_core vdd_core vdd_core all y7 ic ic ic ic ic ic all y8 ic ic ic ic ic ic all y9 pll_pri pll_pri pll_pri pll_pri pll_pri pll_pri all aa1 ic ic ic ic ic ic all aa10icicicic icicall aa11 system_debug system_debug system_debug system_debug system_debug system_debug all aa12 system_rst system_rst system_rst system_rst system_rst system_rst all aa13 gpio[1] gpio[1] gpio[1] gpio[1] gpio[1] gpio[1] all aa14 gpio[2] gpio[2] gpio[2] gpio[2] gpio[2] gpio[2] all aa15 gpio[7] gpio[7] gpio[7] gpio[7] gpio[7] gpio[7] all aa16 gpio[12] gpio[12] gpio[12] gpio[12] gpio[12] gpio[12] all aa17 test_mode[0] test_mode[0] test_mode[0] test_mode[0] test_mode[0] test_mode[0] all aa18 jtag_tdi jtag_tdi jtag_tdi jtag_tdi jtag_tdi jtag_tdi all aa19 ic_gnd ic_gnd ic_gnd ic_gnd ic_gnd ic_gnd all aa20 gnd gnd gnd gnd gnd gnd all aa21 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all aa22 cpu_addr[6] cpu_addr[6] cpu_addr[6] cpu_addr[6] cpu_addr[6] cpu_addr[6] all aa2 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all aa3 gnd gnd gnd gnd gnd gnd all aa4 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all aa5 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all aa6 ic ic ic ic ic ic all aa7 gnd gnd gnd gnd gnd gnd all aa8 a1vdd_pll1 a1vdd_pll1 a1vdd_pll1 a1vdd_pll1 a1vdd_pll1 a1vdd_pll1 all ball # zl50115 signal name zl50116 signal name zl50117 signal name zl50118 signal name zl50119 signal name ZL50120 signal name variant table 2 - zl50115/16/17/18/19/20 ball signal assignment (continued) zl50115/16/17/18/19/20 data sheet 25 zarlink semiconductor inc. nc - not connected - leave open circuit. ic - internally connected - leave open circuit. ic_gnd - internally connected - tie to ground ic_vdd_io - internally connected - tie to vdd_io aa9 ic ic ic ic ic ic all ab1 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all ab10 gpio[3] gpio[3] gpio[3] gpio[3] gpio[3] gpio[3] all ab11 gpio[4] gpio[4] gpio[4] gpio[4] gpio[4] gpio[4] all ab12 gpio[5] gpio[5] gpio[5] gpio[5] gpio[5] gpio[5] all ab13 gpio[6] gpio[6] gpio[6] gpio[6] gpio[6] gpio[6] all ab14 gpio[10] gpio[10] gpio[10] gpio[10] gpio[10] gpio[10] all ab15 gpio[11] gpio[11] gpio[11] gpio[11] gpio[11] gpio[11] all ab16 gpio[13] gpio[13] gpio[13] gpio[13] gpio[13] gpio[13] all ab17 test_mode[2] test_mode[2] test_mode[2] test_mode[2] test_mode[2] test_mode[2] all ab18 ic_gnd ic_gnd ic_gnd ic_gnd ic_gnd ic_gnd all ab19 cpu_addr[2] cpu_addr[2] cpu_addr[2] cpu_addr[2] cpu_addr[2] cpu_addr[2] all ab20 cpu_addr[3] cpu_addr[3] cpu_addr[3] cpu_addr[3] cpu_addr[3] cpu_addr[3] all ab21 cpu_addr[5] cpu_addr[5] cpu_addr[5] cpu_addr[5] cpu_addr[5] cpu_addr[5] all ab22 vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io all ab2 ic ic ic ic ic ic all ab3 ic ic ic ic ic ic all ab4 ic ic ic ic ic ic all ab5 gnd gnd gnd gnd gnd gnd all ab6 ic ic ic ic ic ic all ab7 ic ic ic ic ic ic all ab8 ic ic ic ic ic ic all ab9 gpio[0] gpio[0] gpio[0] gpio[0] gpio[0] gpio[0] all ball # zl50115 signal name zl50116 signal name zl50117 signal name zl50118 signal name zl50119 signal name ZL50120 signal name variant table 2 - zl50115/16/17/18/19/20 ball signal assignment (continued) zl50115/16/17/18/19/20 data sheet 26 zarlink semiconductor inc. 4.0 external interface description the following key applies to all tables: 4.1 tdm interface all tdm interface signals are 5 v tolerant. all tdm interface outputs are high impedance while system reset is low. all tdm interface inputs (including data, clock and frame pul se) have internal pull-down resistors so they can be safely left unconnected if not used. 4.1.1 tdm stream connections there are three interfaces possible among the zl5011x. the zl50117/20 supports four tdm ports [3:0] at 2 mbps, or one tdm port [0] at 8 mbps or one unstructured tdm port [0] for j2/e3/t3/sts-1. the zl50116/19 supports two tdm ports [1:0] at 2 mbps, or one tdm port [0] at 8 mbps (up to 64 ds0). the zl50115/18 supports one tdm port [0] at 2 mbps, or one tdm port [0] at 8 mbps (up to 32 ds0) i input ooutput d internal 100 k ? pull-down resistor present u internal 100 k ? pull-up resistor present t tri-state output signal i/o package balls description tdm_sti[3:0] i d [3] m3 [2] n3 [1] r2 [0] u1 tdm port serial data input streams. for different standards these pins are given different identities: st-bus: tdm_sti[3:0] h.110: tdm_d[3:0] h-mvip: tdm_hds[3:0] triggered on rising edge or falling edge depending on standard. at 8.192 mbps only stream [0] is used. stream [0] is used for unstructured j2, t3/e3 or sts-1 on the zl50117/20. table 3 - tdm interface stream pin definition zl50115/16/17/18/19/20 data sheet 27 zarlink semiconductor inc. note: speed modes: 2.048 mbps - 32 channels per stream. 8.192 mbps - 128 channels per stream. j2 - 98 channels per stream e3 - 537 channels per stream t3 - 699 channels per stream note: all tdm interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely l eft unconnected if not used. tdm_sto[3:0] ot [3] m2 [2] n1 [1] r4 [0] v1 tdm port serial data output streams. for different standards these pins are given different identities: st-bus: tdm_sto[3:0] h.110: tdm_d[3:0] h-mvip: tdm_hds[3:0] triggered on rising edge or falling edge depending on standard. at 8.192 mbps only stream [0] is used. stream [0] is used for unstructured j2, t3/e3 or sts-1 on the zl50117/20. tdm_clki[3:0] i d [3] m1 [2] p1 [1] t1 [0] r3 tdm port clock inputs programmable as active high or low. can accept frequencies of 1.544 mhz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 6.312 mhz or 16.384 mhz depending on standard used. at 8.192 mbps only stream [0] is used. stream [0] is used for unstructured j2, t3/e3 or sts-1 on the zl50117/20. tdm_clko[3:0] ot [3] n2 [2] r1 [1] t2 [0] v2 tdm port clock output s. will generate 1.544 mhz, 2.048 mhz, 4.096 mhz, 6.312 mhz, 8.192 mhz or 16.384 mhz depending on standard used. at 8.192 mbps only stream [0] is used. stream [0] is used for unstructured j2, t3/e3 or sts-1 on the zl50117/20. signal i/o package balls description table 3 - tdm interface stream pin definition zl50115/16/17/18/19/20 data sheet 28 zarlink semiconductor inc. 4.1.2 tdm signals commo n to zl50115/16/17/18/19/20 signal i/o package balls description tdm_clki_ref i d w2 tdm port reference clock input for backplane operation tdm_clko_ref o v3 tdm port reference clock output for backplane operation tdm_frmi_ref i d t3 tdm port reference frame input. for different standards this pin is given a different identity: st-bus: tdm_f0i h.110: tdm_frame h-mvip: tdm_f0 signal is normally active low, but can be active high depending on standard. indicates the start of a tdm frame by pulsing every 125 s. normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. tdm_frmo_ref o w3 tdm port reference frame output. for different standards this pin is given a different identity: st-bus: tdm_f0o h.110: tdm_frame h-mvip: tdm_f0 signal is normally active low, but can be active high depending on standard. indicates the start of a tdm frame by pulsing every 125 s. normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. aux_clki i d l3 auxiliary clock input. typically connected to aux_clko. aux_clko ot l2 auxiliary clock output. typically connected to aux_clki. table 4 - tdm interface common pin definition zl50115/16/17/18/19/20 data sheet 29 zarlink semiconductor inc. 4.2 pac interface all pac interface signals are 5 v tolerant. all pac interface outputs are high impedance while system reset is low. signal i/o package balls description tdm_clkip i d v4 primary reference clock input. should be driven by external clock source to provide locking reference to internal / optional external dpll in tdm master mode. also provides prs clock for rtp timestamps in synchronous modes. acceptable frequency range: 8 khz - 34.368 mhz. tdm_clkis i d u4 secondary reference clock input. backup external reference for automatic switch-over in case of failure of tdm_clkip source. pll_pri ot y9 primary reference output to optional external dpll. multiplexed & frequency divided reference output for support of optional external dpll. expected frequency range: 8 khz - 16.384 mhz. pll_sec ot w10 secondary reference output to optional external dpll multiplexed & frequency divided reference output for support of optional external dpll. expected frequency range: 8 khz - 16.384 mhz. table 5 - pac interface package ball definition zl50115/16/17/18/19/20 data sheet 30 zarlink semiconductor inc. 4.3 packet interfaces for the zl50118/19/20 variants the packet interface is ca pable of either 2 mii inte rfaces, or 1 mii and 1 gmii interfaces, or 1 mii and 1 tbi (1000 mbps) interfaces. the tbi interface is a pcs interface supported by an integrated 1000base-x pcs module. the zl50 118/19/20 supports port 0 and port 1. for the zl50115/16/17 variants the packet interface is ca pable of 1 mii or 1 gmii or 1 tbi (1000 mbps) interface. the tbi interface is a pcs interface supported by an integrated 1000base-x pcs module. the zl50115/16/17 supports port 0. data for all three types of packet switching is based on s pecification ieee std. 802.3 - 2000. only port 0 has the 1000 mbps capability necessary for the gmii/tbi interface. table 6 maps the signal pins used in the mii interface to t hose used in the gmii and tbi interface. table 7 shows all the pins and their related package ball, but is based on the gmi i/mii configuration. all packet interface signals are 5v tolerant, and al l outputs are high impedance while system reset is low. note: m n can be either m0 or m1 for zl5011x variants. mii gmii tbi (pcs) m n _linkup_led m n _linkup_led m n _linkup_led m n _active_led m n _active_led m n _active_led -m n _gigabit_led m n _gigabit_led -m n _refclk m n _refclk m n _rxclk m n _rxclk m n _rbc0 m n _col m n _col m n _rbc1 m n _rxd[3:0] m n _rxd[7:0] m n _rxd[7:0] m n _rxdv m n _rxdv m n _rxd[8] m n _rxer m n _rxer m n _rxd[9] m n _crs m n _crs m n _signal_detect m n _txclk - - m n _txd[3:0] m n _txd[7:0] m n _txd[7:0] m n _txen m n _txen m n _txd[8] m n _txer m n _txer m n _txd[9] -m n _gtx_clk m n _gtx_clk table 6 - packet interface signal mapping - mii to gmii/tbi zl50115/16/17/18/19/20 data sheet 31 zarlink semiconductor inc. signal i/o package balls description m_mdc o h1 mii management data clock. common for all four mii ports. it has a minimum period of 400 ns (maximum freq. 2.5 mhz), and is independent of the txclk and rxclk. m_mdio id/ ot g1 mii management data i/o. common for all four mii ports at up to 2.5 mhz. it is bi-directional between the zl5011x and the ethernet station management entity. data is passed synchronously with respect to m_mdc. table 7 - mii management interface package ball definition mii port 0 signal i/o package balls description m0_linkup_led o g3 led drive for mac 0 to indicate port is linked up. logic 0 output = led on logic 1 output = led off m0_active_led o d17 led drive for mac 0 to indicate port is transmitting or receiving packet data. logic 0 output = led on logic 1 output = led off m0_gigabit_led o e2 led drive for mac 0 to indicate operation at gbps. logic 0 output = led on logic 1 output = led off m0_refclk i d d11 gmii/tbi - reference clock input at 125 mhz. can be used to lock receive circuitry (rx) to m0_gtxclk rather than recovering the rxclk (or rbc0 and rbc1). useful, for example, in the absence of valid serial data. note: in mii mode this pin must be driven with the same clock as m0_rxclk. m0_rxclk i u c10 gmii/mii - m0_rxclk. accepts the following frequencies: 25.0 mhz mii 100 mbps 125.0 mhz gmii 1 gbps table 8 - mii port 0 interface package ball definition zl50115/16/17/18/19/20 data sheet 32 zarlink semiconductor inc. m0_rbc0 i u b9 tbi - m0_rbc0. used as a clock when in tbi mode. accepts 62.5 mhz and is 180c out of phase with m0_rbc1. receive data is clocked at each rising edge of m0_rbc1 and m0_rbc0, resulting in 125 mhz sample rate. m0_rbc1 i u b8 tbi - m0_rbc1 used as a clock when in tbi mode. accepts 62.5 mhz, and is 180 out of phase with m0_rbc0. receive data is clocked at each rising edge of m0_rbc1 and m0_rbc0, resulting in 125 mhz sample rate. m0_col i d a7 gmii/mii - m0_col. collision detection. this signal is independent of m0_txclk and m0_rxclk, and is asserted when a collision is detected on an attempted transmission. it is active high, and only specified for half-duplex operation. m0_rxd[7:0] i u [7] a4 [3] c8 [6] a5 [2] d10 [5] d8 [1] c9 [4] a6 [0] b7 receive data. only half the bus (bits [3:0]) are used in mii mode. clocked on rising edge of m0_rxclk (gmii/mii) or the rising edges of m0_rbc0 and m0_rbc1 (tbi). m0_rxdv / m0_rxd[8] i d c7 gmii/mii - m0_rxdv receive data valid. active high. this signal is clocked on the rising edge of m0_rxclk. it is asserted when valid data is on the m0_rxd bus. tbi - m0_rxd[8] receive data. clocked on the rising edges of m0_rbc0 and m0_rbc1. m0_rxer / m0_rxd[9] i d d6 gmii/mii - m0_rxer receive error. active high signal indicating an error has been detected. normally valid when m0_rxdv is asserted. can be used in conjunction with m0_rxd when m0_rxdv signal is de-asserted to indicate a false carrier. tbi - m0_rxd[9] receive data. clocked on the rising edges of m0_rbc0 and m0_rbc1. mii port 0 signal i/o package balls description table 8 - mii port 0 interface package ball definition (continued) zl50115/16/17/18/19/20 data sheet 33 zarlink semiconductor inc. m0_crs / m0_signal_detect i d b6 gmii/mii - m0_crs carrier sense. this asynchronous signal is asserted when either the transmission or reception device is non-idle. it is active high. tbi - m0_signal detect similar function to m0_crs. m0_txclk i u a3 mii only - transmit clock accepts the following frequencies: 25.0 mhz mii 100 mbps m0_txd[7:0] o [7] c11 [3] b13 [6] d12 [2] b14 [5] b12 [1] d13 [4] c12 [0] c13 transmit data. only half the bus (bits [3:0]) are used in mii mode. clocked on rising edge of m0_txclk (mii) or the rising edge of m0_gtxclk (gmii/tbi). m0_txen / m0_txd[8] o a9 gmii/mii - m0_txen transmit enable. asserted when the mac has data to transmit, synchronously to m0_txclk with the first pre-amble of the packet to be sent. remains asserted until the end of the packet transmission. active high. tbi - m0_txd[8] transmit data. clocked on rising edge of m0_gtxclk. m0_txer / m0_txd[9] o b10 gmii/mii - m0_txer transmit error. transmitted synchronously with respect to m0_txclk, and active high. when asserted (with m0_txen also asserted) the zl5011x will transmit a non-valid symbol, somewhere in the transmitted frame. tbi - m0_txd[9] transmit data. clocked on rising edge of m0_gtxclk. m0_gtx_clk o a8 gmii/tbi only - gigabit transmit clock output of a clock for gigabit operation at 125 mhz. mii port 0 signal i/o package balls description table 8 - mii port 0 interface package ball definition (continued) zl50115/16/17/18/19/20 data sheet 34 zarlink semiconductor inc. mii port 1 (zl50118/19/20 only) signal i/o package balls description m1_linkup_led o c17 led drive for mac 1 to indicate port is linked up. logic 0 output = led on logic 1 output = led off m1_active_led o b15 led drive for mac 1 to indicate port is transmitting or receiving packet data. logic 0 output = led on logic 1 output = led off m1_rxclk i u c4 mii only - receive clock. accepts the following frequencies: 25.0 mhz mii 100 mbps m1_col i d c5 collision detection. this signal is independent of m1_txclk and m1_rxclk, and is asserted when a collision is detected on an attempted transmission. it is active high, and only specified for half-duplex operation. m1_rxd[3:0] i u [3] e1 [1] d1 [2] d3 [0] d2 receive data. clocked on rising edge of m1_rxclk. m1_rxdv i d d5 receive data valid. active high. this signal is clocked on the rising edge of m1_rxclk. it is asserted when valid data is on the m1_rxd bus. m1_rxer i d e4 receive error. active high signal indicating an error has been detected. normally valid when m1_rxdv is asserted. can be used in conjunction with m1_rxd when m1_rxdv signal is de-asserted to indicate a false carrier. m1_crs i d f2 carrier sense. this asynchronous signal is asserted when either the transmission or reception device is non-idle. it is active high. m1_txclk i u e3 mii only - transmit clock accepts the following frequencies: 25.0 mhz mii 100 mbps m1_txd[3:0] o [3] c1 [1] b5 [2] b1 [0] b4 transmit data. clocked on rising edge of m1_txclk. m1_txen o a2 transmit enable. asserted when the mac has data to transmit, synchronously to m1_txclk with the first pre-amble of the packet to be sent. remains asserted until the end of the packet transmission. active high. table 9 - mii port 1 interface package ball definition zl50115/16/17/18/19/20 data sheet 35 zarlink semiconductor inc. 4.4 cpu interface all cpu interface signals are 5 v tolerant. all cpu interface outputs are high impedance while system reset is low. m1_txer o c6 transmit error. transmitted synchronously with respect to m1_txclk, and active high. when asserted (with m1_txen also asserted) the zl5011x will transmit a non-valid symbol, somewhere in the transmitted frame. signal i/o package balls description cpu_data[31:0] i/ ot [31] c16 [15] e21 [30] e19 [14] e22 [29] c18 [13] b19 [28] a11 [12] a17 [27] b16 [11] g21 [26] c19 [10] h19 [25] d20 [9] a18 [24] a12 [8] a19 [23] a14 [7] a20 [22] b17 [6] d22 [21] e20 [5] j20 [20] b18 [4] h21 [19] a16 [3] j21 [18] f20 [2] k20 [17] f21 [1] h20 [16] f22 [0] g22 cpu data bus. bi-directional data bus, synchronously transmitted with cpu_clk rising edge. note: as with all ports in the zl5011x device, cpu_data[0] is the least significant bit (lsb). cpu_addr[23:2] i [23] d21 [11] r20 [22] n20 [10] v21 [21] p22 [9] v22 [20] r22 [8] w22 [19] n22 [7] y22 [18] p21 [6] aa22 [17] p20 [5] ab21 [16] t22 [4] w21 [15] u21 [3] ab20 [14] t21 [2] ab19 [13] r21 [12] u22 cpu address bus. address input from processor to zl5011x, synchronously transmitted with cpu_clk rising edge. note: as with all ports in the zl5011x device, cpu_addr[2] is the least significant bit (lsb). table 10 - cpu interface package ball definition mii port 1 (zl50118/19/20 only) signal i/o package balls description table 9 - mii port 1 interface package ball definition (continued) zl50115/16/17/18/19/20 data sheet 36 zarlink semiconductor inc. cpu_cs i u n21 cpu chip select. synchronous to rising edge of cpu_clk and active low. is asserted with cpu_ts _ale. must be asserted with cpu_oe to asynchronously enable the cpu_data output during a read, including dma read. cpu_we i m21 cpu write enable. synchronously asserted with respect to cpu_clk rising edge, and active low. used for cpu writes from the processor to registers within t he zl5011x. asserted one clock cycle after cpu_ts _ale. cpu_oe i m22 cpu output enable. synchronously asserted with respect to cpu_clk rising edge, and active low. used for cpu reads from the processor to registers within the zl5011x. asserted one clock cycle after cpu_ts _ale. must be asserted with cpu_cs to asynchronously enable the cpu_data output during a read, including dma read. cpu_ts _ale i m20 synchronous input with rising edge of cpu_clk. latch enable (ale), active high signal. asserted with cpu_cs , for a single clock cycle. cpu_sdack1 i a21 cpu/dma 1 acknowledge input. active low synchronous to cpu_clk rising edge. used to acknowledge request from zl5011x for a dma write transaction. only used for dma transfers, not for normal register access. cpu_sdack2 i l21 cpu/dma 2 acknowledge input active low synchronous to cpu_clk rising edge. used to acknowledge request from zl5011x for a dma read transaction. only used for dma transfers, not for normal register access. cpu_clk i l19 cpu powerquicc? ii bus interface clock input. 66 mhz clock, with minimum of 6 ns high/low time. used to time all host interface signals into and out of zl5011x device. signal i/o package balls description table 10 - cpu interface package ball definition (continued) zl50115/16/17/18/19/20 data sheet 37 zarlink semiconductor inc. cpu_ta ot b22 cpu transfer acknowledge. driven from tri-state condition on the negative clock edge of cpu_clk following the assertion of cpu_cs. active low, asserted from the rising edge of cpu_clk. for a read, asserted when valid data is available at cpu_data. the data is then read by the host on the following rising edge of cpu_clk. for a write, is asserted when the zl5011x is ready to accept data from the host. the data is written on the rising edge of cpu_clk following the assertion. returns to tri-state from the negative clock edge of cpu_clk following the de-assertion of cpu_cs. cpu_dreq0 ot k22 cpu dma 0 request output active low synchronous to cpu_clk rising edge. asserted by zl5011x to request the host initiates a dma write. only used for dma transfers, not for normal register access. cpu_dreq1 ot c22 cpu dma 1 request active low synchronous to cpu_clk rising edge. asserted by zl5011x to indicate packet data is ready for transmission to the cpu, and request the host initiates a dma read. only used for dma transfers, not for normal register access. cpu_ireqo o j22 cpu interrupt 0 request (active low) cpu_ireq1 o g20 cpu interrupt 1 request (active low) signal i/o package balls description table 10 - cpu interface package ball definition (continued) zl50115/16/17/18/19/20 data sheet 38 zarlink semiconductor inc. 4.5 system function interface all system function interface signals are 5 v tolerant. the core of the chip will be held in reset for 16 383 system_clk cycles after system_rst has gone high to allow the pll?s to lock. 4.6 test facilities 4.6.1 administration, control and test interface all administration, control and test interface signals are 5 v tolerant. signal i/o package balls description system_clk i w13 system clock input. the system clock frequency is 100 mhz. the frequency must be accurate to within 32 ppm in synchronous mode. system_rst i aa12 system reset input. active low. the system reset is asynchronous, and causes all registers wi thin the /1/4 to be reset to their default state. system_debug i aa11 system debug enable. this is an asynchronous signal that, when de-asserted, prevents the software assertion of the debug-freeze command, regardless of the internal state of registers, or any erro r conditions. active high. table 11 - system function interface package ball definition signal i/o package balls description gpio[15:0] id/ ot [15] w17 [7] aa15 [14] y16 [6] ab13 [13] ab16 [5] ab12 [12] aa16 [4] ab11 [11] ab15 [3] ab10 [10] ab14 [2] aa14 [9] w15 [1] aa13 [8] y15 [0] ab9 general purpose i/o pins. connected to an internal register, so customer can set user-defined parameters. bits [4:0] reserved at start-up or reset for memory tdl setup. see the zl50115/16/17/18/19/20 programmers model for more details. recommend 5 kohm pulldown on these signals. test_mode[2:0] i d [2] ab17 [1] y17 [0] aa17 test mode input - ensure these pins are tied to ground for normal operation. 000 sys_normal_mode 001-010 reserved 011 sys_tristate_mode 100-111 reserved table 12 - administration/control interface package ball definition zl50115/16/17/18/19/20 data sheet 39 zarlink semiconductor inc. 4.6.2 jtag interface all jtag interface signals are 5 v tolerant, and conform to the requirements of ieee1149.1 (2001). 4.7 miscellaneous inputs the following unused inputs must be tied low or high as appropriate. signal i/o package balls description jtag_trst i u y18 jtag reset. asynchronous reset. in normal operation this pin should be pulled low. jtag_tck i v20 jtag clock - maximum frequency is 25mhz, typically run at 10 mhz. in normal operation this pin should be pulled either high or low. jtag_tms i u u20 jtag test mode select. synchronous to jtag_tck rising edge. used by the test access port controller to set certain test modes. jtag_tdi i u aa18 jtag test data input. synchronous to jtag_tck. jtag_tdo o w20 jtag test data output. synchronous to jtag_tck. table 13 - jtag interface package ball definition signal package balls description ic_gnd w11, y11, y19, aa19, ab18 internally connected. tie to gnd. ic_vdd_io l22 internally connected. tie to vdd_io. table 14 - miscellaneous inputs package ball definitions zl50115/16/17/18/19/20 data sheet 40 zarlink semiconductor inc. 4.8 power and ground connections signal package balls description vdd_io a1 a22 aa2 aa21 aa4 aa5 ab1 ab22 b2 b21 c14 c15 c20 c3 d16 d19 d4 d7 g19 g4 k4 m4 n19 p3 t19 t20 t4 u2 w16 w19 w4 w5 w7 w8 y20 y3 3.3 v vdd power supply for io ring gnd a13 a15 aa20 aa3 aa7 ab5 b11 b20 b3 c2 c21 h2 j10 j11 j12 j13 j14 j9 k10 k11 k12 k13 k14 k19 k9 l1 l10 l11 l12 l13 l14 l20 l9 m10 m11 m12 m13 m14 m19 m9 n10 n11 n12 n13 n14 n9 p10 p11 p12 p13 p14 p2 p9 r19 u3 w12 y13 y14 y2 y21 0 v ground supply vdd_core d14 d15 d18 d9 f19 f4 h4 j19 j4 l4 n4 p19 p4 u19 w14 w6 w9 y6 1.8 v vdd power supply for core region a1vdd aa8 1.8 v pll power supply table 15 - power and ground package ball definition zl50115/16/17/18/19/20 data sheet 41 zarlink semiconductor inc. 4.9 internal connections the following pins are connected internally, and must be left open circuit. 4.10 no connections the following pins are not connected inte rnally, and should be left open circuit. 4.11 device id signal package balls description ic aa1 aa10 aa6 aa9 ab2 ab3 ab4 ab6 ab7 ab8 h22 k21 w1 y1 y10 y12 y4 y5 y7 y8 internally connected. leave open circuit table 16 - internal connections package ball definitions signal package balls description nc f1 h3 j1 j2 j3 k1 k2 k3 no connection. leave open circuit. table 17 - miscellaneous inputs package ball definitions signal i/o package balls description device_id[4:0] o [4] a10 [3] v19 [2] w18 [1] f3 [0] g2 device id. zl50115 = 00000 zl50116 = 00001 zl50117 = 00010 zl50118 = 00011 zl50119 = 00100 ZL50120 = 00101 table 18 - device id ball definition zl50115/16/17/18/19/20 data sheet 42 zarlink semiconductor inc. 5.0 typical applications 5.1 leased line provision circuit emulation is typically used to support the provisi on of leased line services to customers using legacy tdm equipment. for example, figure 8 shows a leased line tdm service being carried across a packet network. the advantages are that a carrier can upgr ade to a packet switched network, whilst still mainta ining their existing tdm business. the zl5011x is capable of handling circuit emulation of bo th structured t1, e1, and j2 links (e.g., for support of fractional circuits) and unstructured (or clear channel) t1, e1, j2, t3 and e3 links. the device handles the data-plane requirements of the provider edge inter-working function (with the exception of the physical interfaces and line interface units). control plane functions are fo rwarded to the host processor controlling the zl5011x device. the zl5011x provides a per-stream clock recovery func tion to reproduce the tdm se rvice frequency at the egress of the packet network. this is requir ed otherwise the queue at the egress of th e packet network will either fill up or empty, depending on whether the regenerated clock is slower or faster than the original. figure 8 - leased line services over a circuit emulation link carrier network customer premises customer premises extract clock customer data ~ ~ f service f service tdm packet network tdm customer data tdm to packet f service provider edge interworking function provider edge interworking function queue zl50115/16/17/18/19/20 data sheet 43 zarlink semiconductor inc. 5.2 remote concentrator unit the remote concentrator application, shown in figure 9, consists of a remote concentrators connected to the central office (co) by a dedicated fiber link running gi gabit ethernet (ge) or ether net over sonet (eos) rather than by nxt1/e1 or ds3/e3. the remote concentrators provide both tdm service and native ethernet service to the multi-tenet unit or multi-dwelling unit (mtu/mdu). the zl5011x is used to emulate tdm circuits over ethernet by establishing cesop connections between the remote concentrator and the co. the nat ive ip or ethernet traffic is multiple xed with the cesop traffic inside the remote concentrator and sent across the same ge connection to the co. at the co the native ip or ethernet traffic is split from the cesop connections at sent towards th e packet network. multiple t1/e1 cesop connections from several remote concentrators are aggregated in the co using a larger zl5011x variant, converted back to tdm circuits, and connected to the pstn through a higher bandwidth tdm circuit such as oc-3 or stm-1. the use of cesop here allows the convergence of voice and data on a single access network based on ethernet. this convergence on ethernet, a packet technology, ra ther than sonet/sdh, a sw itched circuit technology, provides cost and operational savings. figure 9 - remote concentrator unit using cesop zl50115/16/17/18/19/20 data sheet 44 zarlink semiconductor inc. 5.3 fttp the fiber to the premise (fttp) application, shown in fi gure 10, consists of an ethernet passive optical network (epon) deployed in the wide area network (wan). the optical network units (onu) sit at the curb while the optical line terminals (olt) are located at the centra l office (co). the onus are traditionally equipped with ethernet interfaces to provide video and data service to the customer premise. the onu includes a zl5011x which enables the box to provide t1/e1 service to the customer. the zl5011x is used to establish cesop connections between the onu and t he olt to transparently carry tdm circuits across the epon. the onu would use a smaller variant of the zl5011 x and the olt would use a la rger variant to aggregate cesop traffic from many onus and connect them at the co to the pstn. the native ip or ethernet traffic from the onu would be split off at the olt and connected to the packet network. figure 10 - epon using cesop fiber links olt pstn ip t1/e1 gige over fiber onu ethernet t1/e1 onu ethernet t1/e1 onu ethernet t1/e1 optical splitter ethernet customer premises cesop zl50115/16/17/18/19/20 data sheet 45 zarlink semiconductor inc. 5.4 wireless - wifi or wimax the wireless application, show n in figure 11, may either be in the form of wimax for broadband access or wi-fi for smaller-scale loans. both technologies carry ethernet ov er radio links between sites or pieces of equipment. an application for cesop technology over a wimax network is to enable the service provider to sell t1/e1 service in addition to video and data services that are natively carried across the wimax connection. a zl5011x is used at the customer premise to packetize th e t1/e1, fractional t1/e1 or tdm circuit into ethernet packets, which are transported back to the central office (co). at the co the tdm circuit is re-assembl ed from the ethernet packets and send to the pstn. the cesop traffic is converged onto the same wimax conne ction as the native ethernet traffic for video and data. an application for cesop technology over a wi-fi network is to enable a distributed pbx system in either a single building or between buildings in a campus environmen t. in this application the t1/e1 connection from a pbx is connected using a cesop to another pbx. a wireless site -to-site cesop connection between buildings in a campus would allow for deployment savings against havi ng to run dedicated copper cables between buildings. figure 11 - wi-fi and wimax using cesop wireless lan access point wireless lan access point wireless lan access point wireless lan access point wimax (802.16) wi-fi (802.11) wi-fi mac cesop t1/e1 wi-fi mac cesop t1/e1 54 mbps up to 100 m wimax mac cesop t1/e1 70 mbps up to 48 km wimax mac cesop t1/e1 cesop cesop zl50115/16/17/18/19/20 data sheet 46 zarlink semiconductor inc. 5.5 digital loop carrier the broadband digital loop carrier (bbdlc ) application, shown in figure 12, consists of a bbdlc connected to the central office (co) by a dedicate d fiber link running gigabit ethernet (ge) rather than by nxt1/e1 or ds3/e3. the zl5011x is used to emulate tdm circuits over ethernet by establishing cesop connections between the bbdlc and the co. at the co the native ip or ethernet traf fic is split from the cesop connections at sent towards the packet network. multiple t1/e1 cesop connections from several bbdlc are aggregated in the co using a larger zl5011x variant, converted bac k to tdm circuits, and connected to a class 5 switch destined towards the pstn. in this configuration t3/e3 services can also be prov ided. using cesop allows voice and data traffic to be converged onto a single link. figure 12 - digital loop carrier using cesop dedicated fiber links central office t1/e1 n x t1/e1 pstn ip broadband dlc pots digital loop carrier gige over fiber central office switch (class 5) ip edge router or multi-service switching platform n x gige gige over fiber cesop zl50115/16/17/18/19/20 data sheet 47 zarlink semiconductor inc. 5.6 integrated access device the integrated access device (iad) application consists of an iad located at the curb or customer premise with an ethernet connection to an tdm aggregation box sitting in the access area of the network. the zl5011x in the iad modem packetizes the t1/e1 or fr actional t1/e1 tdm circuit into ethernet cesop packets. the cesop traffic is multiplexed with the native ethernet data traffic from the iad?s et hernet ports onto the ethernet link to the aggregation equipment. the aggr egator will split off the native ethernet tr affic from multiple iads and send the traffic on to packet network. the aggregator will contain a larger zl5011x th at will terminate multiple cesop connections from multiple iads and send the tdm circuits to the pstn, perhaps over a higher bandwidth tdm pipe such as ds3. the use of cesop in this application allows the iad to support both native ethernet service as well as t1/e1 service in the same box, while converging both types of traffic onto a single ethernet connection back towards the provider. figure 13 - integrated access device using cesop 6.0 functional description the zl5011x family provides the data-plane processing to enable constant bit rate tdm services to be carried over a packet switched network, such as an ethernet, ip or mpls network. the device segments the tdm data into user-defined packets, and passes it transparently over t he packet network to be reconstructed at the far end. this has a number of applications, in cluding emulation of tdm circuits and packet backplanes for tdm-based equipment. figure 14 - zl50115/16/17/ 18/19/20 family operation tdm aggregation n x t1/e1 pstn ip small business iad central office switch (class 5) ip edge router or multi-service switching platform n x gige cesop ethernet link ethernet t1/e1 small business iad ethernet link ethernet t1/e1 constant bit rate tdm link packet switched network constant bit rate tdm link cesop tdm-packet conversion cesop tdm-packet conversion tdm equipment tdm equipment interworking function interworking function transparent data flow between tdm equipment zl50115/16/17/18/19/20 data sheet 48 zarlink semiconductor inc. 6.1 block diagram a diagram of the zl5011x device is given in figure 15, which shows the major data flows between functional components. figure 15 - zl50115/16/17/18/19/20 data and control flows 6.2 data and control flows there are numerous combinations that can be implem ented to pass data through the zl5011x device depending on the application requirements. the task manager can be considered the central pivot, through which all flows must operate. the task manager acts as a ?router? in the centre of the chip , directing packets to the appropriate blocks for further processing. the task message contains a point er to the relevant data, instructions as to what to do with the data, and ancillary information about the packe t. effectively this means the flow of data through the device can be programmed, by setting the task message contents appropriately. flow number flow through device 1 tdm to (tm) to pe to (tm) to pkt 2 pkt to (tm) to pe to (tm) to tdm 3 tdm to (tm) to pkt 4 pkt to (tm) to tdm 5 tdm to (tm) to cpu 6 tdm to (tm) to pe to (tm) to cpu 7 cpu to (tm) to tdm 8 pkt to (tm) to cpu 9 cpu to (tm) to pkt 10 1 tdm to (tm) to tdm 11 1 1. this flow is for loopback and may be helpful for test purposes pkt to (tm) to pkt table 19 - standard device flows 4 t1, 4 e1, 1 j2, 1 t3, 1 e3 or 1 sts-1 ports h.110, h-mvip, st-bus backplanes single 100 mbps mii fast ethernet and/o r single 1000 mbps (g)mii/tbi gigabit ethernet motorola powerquicc tm compatible jtag interface dual packet interface mac tdm formatter payload assembly tdm interface packet receive packet transmit admin. clock recovery jtag test controller central task manager host interface dma control data flows control flows protocol engine memory management unit on-chip ram controller zl50115/16/17/18/19/20 data sheet 49 zarlink semiconductor inc. each of the 11 data flows uses the task manager to ro ute packet information to the next block or interface for onward transmission. the flow is determined by the ty pe field in the task message (see zl50115/16/17/18/19/20 programmers model). 6.3 tdm interface the zl5011x family offers the following types of tdm service across the packet network: unstructured services are fully asynchronous, and include full support for clock recove ry on a per stream basis. both adaptive and differential clock recovery mechanisms can be used. structured services are synchronous, with all streams driven by a common clock and frame reference. these services can be offered in two ways: ? synchronous master mode - the zl5011x provides a common clock and frame pulse to all streams, which may be locked to an incoming clock or frame reference ? synchronous slave mode - the zl5011x accepts a common external clock and frame pulse to be used by all streams in either structured mode, n x 64 kbps trunking is supported as detailed in ?payload order? on page 53. 6.3.1 tdm interface block the tdm interface contains two basic types of interface: unstructured clock and data, fo r interfacing directly to a line interface unit; or structured, framed data, for interfacing to a framer or tdm backplane. unstructured data is treated asynchronously, with every st ream using its own clock. clock recovery is provided on each output stream, to reproduce the tdm service frequency at the egress of the packet network. structured data is treated synchronously, i.e. all data streams are timed by the same clock and frame references. these can either be supplied from an external source (slave mode) or gener ated internally using the on-chip stratum 3/4/4e pll (master mode). service type tdm interface interface type interfaces to unstructured asynchronous t1, e1, j2, e3, t3 and sts-1 bit clock in and out data in and out line interface unit structured synchronous (n x 64 kbps) t1, e1 and j2 framed tdm data streams at 2.048 and 8.192 mbps bit clock out frame pulse out data in and out framers tdm backplane (master) bit clock in frame in data in and out framers tdm backplane (slave) table 20 - tdm services offered by the zl50115/16/17/18/19/20 family zl50115/16/17/18/19/20 data sheet 50 zarlink semiconductor inc. 6.3.2 structured tdm port data formats the zl5011x is programmable such that the frame/clock polarity and clock alignment can be set to any desired combination. table 21 shows a brief summary of four di fferent tdm formats; st-bus, h.110, h-mvip, and generic (synchronous mode only), for more information see the relevant specifications shown. there are many additional formats for tdm transmission not depicted in table 21, but t he flexibility of the port will cover almost any scenario. the overall data format is set for the entire tdm interface device, rather than on a per st ream basis. it is possible to control the polarity of the master clock and frame pulse outputs, independent of the chosen data format (used when operating in synchronous master mode). data format data rate (mbps) number of channels per frame clock freq. (mhz) nominal frame pulse width (ns) frame pulse polarity frame boundary alignment standard clock frame pulse st-bus 2.048 32 2.048 244 negative rising edge straddles boundary msan-126 rev b (issue 4) zarlink 2.048 32 4.096 244 negative falling edge straddles boundary 8.192 128 16.384 61 negative falling edge straddles boundary h.110 8.192 128 8.192 122 negative rising edge straddles boundary ectf h.110 h-mvip 2.048 32 2.048 244 negative rising edge straddles boundary h-mvip release 1.1a 2.048 32 4.096 244 negative falling edge straddles boundary 8.192 128 16.384 244 negative falling edge straddles boundary generic 2.048 32 2.048 488 positive rising edge rising edge of clock 8.192 128 8.192 122 positive rising edge rising edge of clock table 21 - some of the tdm port formats accepted by the zl50115/16/17/18/19/20 family zl50115/16/17/18/19/20 data sheet 51 zarlink semiconductor inc. 6.3.3 tdm clock structure the tdm interface can operate in two modes, synchronou s for structured tdm data, and asynchronous for unstructured tdm data. the zl5011x is capable of provid ing the tdm clock for either of the modes. the zl5011x supports clock recovery in both synchronous and asynch ronous modes of operation. in asynchronous operation each stream may have independent clock recovery. 6.3.3.1 synchronou s tdm clock generation in synchronous mode all 4 streams will be driven by a common clock source. when t he zl5011x is acting as a master device, the source can either be the internal dpll or an external pll. in both cases, the primary and secondary reference clocks are taken from either two tdm input clocks, or two external clock sources driven to the chip. the input clocks are then divided down where necessary and sent either to the inte rnal dpll or to the output pins for connection to an external dpll. the dpll th en provides the common cloc k and frame pulse required to drive the tdm streams. see ?dpll specif ication? on page 60 for further details. figure 16 - synchronous tdm clock generation when the zl5011x is acting as a slave device, the common clock and frame pulse signals are taken from an external device providing the tdm master function. 6.3.3.2 asynchronous tdm clock generation each stream uses a separate internal dco to provide an asynchronous tdm clock output. the dco can be controlled to recover the clock from the original tdm source depending on the timing algorithm used. 6.4 payload assembly data traffic received on the tdm interface is sampled in the tdm interface block, and synchronized to the internal clock. it is then forwarded to the payload assembly pr ocess. the zl5011x payload assembler can handle up to 128 active packet streams or ?contexts? simultaneously. each co ntext generates a single stream of packets identified by a label in the packet header known as the "context id". packet payloads are assembled in the format shown in figure 17 - on page 52 in structured operation. this meets the requirements of the cesopsn standard under development in the ietf. alternatively, packet paylo ads are assembled in the format shown in figure 19 on page 52. this format meets the requirements of th e satop standard under development in the ietf. when the payload has been assembled it is written in to the centrally managed memory, and a task message is passed to the task manager. frame clock tdm_clki[3:0] pll_se c pll_pri srs srd div div internal dpll prs prd tdm_clkip tdm_clkis zl50115/16/17/18/19/20 data sheet 52 zarlink semiconductor inc. 6.4.1 structured payload operation in structured mode a context may contain any number of 64 kbps channels. these channels need not be contiguous and they may be selected from any input stream. channels may be added or deleted dynamically from a context. this feature can be used to optimize bandwidth utilisation. modifications to the context are synchronised with the start of a new packet. the fixed header at the start of each packet is added by the pa cket transmit block. this consists of up to 64 bytes, containing the ethernet header, any upper layer protocol headers, and the two byte context descriptor field (see section below). the header is entirely user pr ogrammable, enabling the use of any protocol. the payload header and size must be chosen so that the over all packet size is not less than 64 bytes, the ethernet standard minimum packet size. where this is likely to be the case, the header or data must be padded (as shown in figure 17 and figure 19) to ensure the packet is la rge enough. this padding is added by the zl5011x for most applications. figure 17 - zl50115/16/17/18/19/20 packet format - structured mode in applications where large payloads are being used, the payload size must be chosen such that the overall packet size does not exceed the maximum ethernet packet size of 1518 bytes (1522 bytes with vlan tags). figure 17 shows the packet format for structured tdm data, where the payload is split into frames, and each frame concatenated to form the packet. channel 1 channel 2 channel x data for tdm frame 1 heade r ethernet fcs tdm payload (constructed by payload assembler) data for tdm frame n channel 1 channel 2 channel x data for tdm frame 2 channel 1 channel 2 channel x ethernet header network layers (added by packet transmit) upper layers (added by protocol engine) e.g. ipv4, ipv6, mpls e.g. udp, l2tp, rtp, cesopsn, satop may include vlan tagging static padding (if required to meet minimum payload size) may also be placed in the packet header zl50115/16/17/18/19/20 data sheet 53 zarlink semiconductor inc. 6.4.1.1 payload order packets are assembled sequentially, with each channel placed into the packet as it arrives at the tdm interface. a fixed order of channels is maintained (see figure 18), with channel 0 placed before channel 1, which is placed before channel 2. it is this order that allows the packet to be correctly disassembled at the far end. a context must contain only unique channel numbers. as such a context that contains the same channel from different streams, for example channel 1 from stream 2 and channel 1 from stream 3, would not be permitted. figure 18 - channel order for packet formation each packet contains one or more frames of tdm data, in sequential order. this groups the selected channels for the first frame, followed by the same set of channels for the subsequent frame, and so on. 6.4.2 unstructured payload operation in unstructured mode, the payload is not split by defined fram es or timeslots, so the packet consists of a continuous stream of data. each packet consists of a number of oc tets, as shown in figure 19. the number of octets in a packet need not be an integer number of frames. a typi cal value for n may be 192, as defined in the ietf pwe3 standard." for example, consider mapping the unstructured data of a 25 timeslot ds0 stream. the data for each t1 frame would normally consist of 193 bits, 192 data bits and 1 framin g bit. if the payload consists of 24 octets it will be 1 bit short of a complete frames worth of data, if the payload cons ists of 25 octets it will be 7 bits over a complete frames worth of data. note: no alignment of the octets with the t1 framing structure can be assumed. figure 19 - zl50115/16/17/18/19/20 packet format - unstructured mode channel 0 channel 1 channel 2 channel 31 stream 0 channel 0 channel 1 channel 2 channel 31 stream 3 channel 0 channel 1 channel 2 channel 31 stream 1 channel 0 channel 1 channel 2 channel 31 stream 2 channel assembly order heade r n octets of data from unstructured stream note: no frame or channel alignmen t may include vlan tagging e.g. ipv4, ipv6, mpls e.g. udp, l2tp, rtp, cesopsn, satop tdm payload (constructed by payload assembler) 46 to 1500 bytes may also be placed in the packet header octet 1 octet 2 octet n ethernet heade r network layers (added by packet transmit) upper layers (added by protocol engine) ethernet fcs static padding (if required to meet minimum payload size) zl50115/16/17/18/19/20 data sheet 54 zarlink semiconductor inc. 6.5 protocol engine in general, the next processing block for tdm packets is the protocol engine. this handles the data-plane requirements of the main higher level pr otocols (layers 4 and 5) expected to be used in typical applications of the zl5011x family: udp, rtp, l2tp, cesopsn, satop and cdp. the protocol engine can add a header to the datagram containing up to 24 bytes. this header is lar gely static information, and is programmed directly by the cpu. it may contain a number of dynamic fields, incl uding a length field, checksum, sequence number and a timestamp. the location, and in some cases the length of these fields is also progra mmable, allowing the various protocols to be placed at variable locations within the header. 6.6 packet transmission packets ready for transmission are queued to the switch fabric interface by the queue manager. four classes of service are provided, allowing some packet streams to be prioritized over others. on transmission, the packet transmit block appends a programmable header, which has been set up in advance by the control processor. typically this contains the data-link and network layer heade rs (layers 2 and 3), such as ethernet, ip (versions 4 and 6) and mpls. 6.7 packet reception incoming data traffic on the packet interface is received by the macs. the well-formed packets are forwarded to a packet classifier to determi ne the destination. when a packet is succes sfully classified the destination can be the tdm interface, the lan interface or the host interface. tdm traffic is then further classified to determine the context it is intended for. each tdm interface context has an individual queue, and the tdm re-formatting proce ss re-creates the tdm streams from the incoming packet streams. this queue is used as a jitter bu ffer, to absorb variation in packet delay across the network. the size of the jitter buffer can be pr ogrammed in units of tdm frames (i.e., steps of 125 s). there is also a queue to the host interface, allowing a tr affic flow to the host cpu for processing. the host?s dma controller can be used to retrieve packet data and write it out into the cpu?s own memory. 6.8 tdm formatter at the receiving end of the packet network, the origin al tdm data must be re-constructed from the packets received. this is known as re-formatting, and follows t he reverse process from the payload assembler. the tdm formatter plays out the packets in the correct sequence, di recting each octet to the selected timeslot on the output tdm interface. when lost or late packets are detected, the tdm format ter plays out underrun data for the same number of tdm frames as were included in the missing packet. underrun data can either be the last value played out on that timeslot, or a pre-programmed value (e.g., 0xff). if the pack et subsequently turns up it is discarded. in this way, the end-to-end latency through the system is maintained at a constant value. 6.9 ethernet traffic aggregation (zl50118/19/20 only) the zl5011x allows native ethernet traffic received on t he customer side fast ether net port to be aggregated with the cesop traffic from the tdm interface to the provider side gigabit ethernet port. likewise, traffic from the provider side gigabit ethernet port may be split between cesop traffic destined towards the tdm interface and native ethernet traffic destined toward s the customer side fast ethernet por t. this functionality is achieved by correctly programming the task manager and packet classifiers for flow 11. from the provider side gigabi t ethernet port to the customer side td m and fast ethernet interfaces there is sufficient internal bandwidth to avoid any prioritiza tion issues. from the customer side tdm and fast ethernet interfaces towards the gigabit ethernet ports the tdm c esop traffic may be sent to a higher priority output queue (there are four output queues total) than the native fast ethernet traffic. in this way the access to the provider side gigabit ethernet port is prioritized for tdm traffic over native ethernet traffic. zl50115/16/17/18/19/20 data sheet 55 zarlink semiconductor inc. 7.0 clock recovery one of the main issues with circuit em ulation is that the clock used to drive the tdm link is not necessarily linked into the central office reference clock, and hence may be any value within the tolerance defined for that service. the reverse link may also be independently timed, and operating at a slightly different frequency. in the plesiochronous digital hierarchy the difference in clock frequencies between tdm links is compensated for using bit stuffing techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network. with a packet network, that connection between the i ngress and egress frequency is broken, since packets are discontinuous in time. from figur e 8, the tdm service frequency f service at the customer premises must be exactly reproduced at the egress of the packet network. the consequence of a long -term mismatch in frequency is that the queue at the egress of t he packet network will either fill up or empty, depending on whether the regenerated clock is slower or faster than the original. this will cause loss of data and degradation of the service. the zl5011x provides a per-stream clock recovery func tion to reproduce the tdm se rvice frequency at the egress of the packet network. there are two schemes are employ ed, depending on the availabili ty of a common reference clock at each provider edge unit, within the zl5011x - differential and adaptive. the clock recovery itself is performed by software in the external processor, wi th support from on-chip har dware to gather the required statistics. 7.1 differential clock recovery for applications where the wander characteristics of th e recovered clock are very important, such as when the emulated circuit must be connected into the plesiochronou s digital hierarchy (pdh), the zl5011x also offers a differential clock recovery technique. this relies on ha ving a common reference clock available at each provider edge point. figure 20 illustrates this concept with a common primary reference source (prs) clock being present at both the source and destination equipment. in a differential technique, the timing of the tdm service cl ock is sent relative to the common reference clock. since the same reference is available at the packet egress point and the packet size is fixed, the original service clock frequency can be recovered. this technique is unaffected by any low frequency components in the packet delay variation. the disadvantage is the requirement for a comm on reference clock at each end of the packet network, which could either be the central offi ce tdm clock, or provided by a glo bal position system (gps) receiver. figure 20 - differential clock recovery liu liu zl5011x source node zl5011x destination node timestamp generation timestamp extraction host cpu timing recovery dco data source clock data dest'n clock packets packets prs clock network zl50115/16/17/18/19/20 data sheet 56 zarlink semiconductor inc. 7.2 adaptive clock recovery for applications where there is no common reference clock between provider edge units, an adaptive clock recovery technique is provided. this infers the clock rate of the original tdm service clock from the mean arrival rate of packets at the packet egress point. the disadvantage of this type of scheme is that, depending on the characteristics of the packet network, it may prove difficult to regenerate a clock that stays within the wa nder requirements of t he plesiochronous digital hierarchy (specifically mtie). the reason for this is that any variation in delay between packets will feed through as a variation in the frequency of the re covered clock. high frequency jitter can be filtered out, but any low frequency variation or wander is more diff icult to remove without a very long time constant. this will in turn affect the ability of the system to lock to the original clock within an acceptable time. with no prs clock the only information available to de termine the tdm transmission speed is the average arrival rate of the packets, as shown in figure 21. timestamps representing the number of elapsed source clock periods may be included in the packet header, or information can be inferred from a known payload size at the destination. it is possible to maintain average buffer-fill levels at the destination, where an increase or decrease in the fill level of the buffer would require a change in transmission clock spee d to maintain the average. a dditionally, the buffer-fill depth can be altered independently, with no relation to the recovered clock frequency, to control tdm transmission latency. figure 21 - adaptive clock recovery 8.0 system features 8.1 latency the following lists the intrinsic processing latency of th e zl5011x. the intrinsic processing latency is dependent on the number of channels in a context for structured operati on, as detailed below. however, the intrinsic processing latency is not dependent on the total number of contexts opened or the total number of channels being processed by the device. ? tdm to packet transmission processing latency less than 125 s ? packet to tdm transmission processing latency less than 250 s (unstructured) ? packet to tdm transmission processing latency less than 250 s (structured, more than 16 channels in context) ? packet to tdm transmission processing latency less than 375 s (structured, 16 or less channels in context) liu liu zl5011x source node zl5011x destination node host cpu queue monitor dco data source clock data dest'n clock packets packets network zl50115/16/17/18/19/20 data sheet 57 zarlink semiconductor inc. end-to-end latency may be estimated as the transmit la tency + packet network latency + receive latency. the transmit latency is the sum of the transmit processing and the num ber of frames per packet x 125 s. the receive latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to compensate for packet network pdv. the zl5011x is capable of creating an extremely low lat ency connection, with end to end delays of less than 0.5 ms, depending on us er configuration. 8.2 loopback modes the zl5011x devices support loopback of the td m circuits and the circ uit emulation packets. tdm loopback is achieved by first packetizing the tdm circuit as normal via the tdm interface and payload assembly blocks. the packetized data is then routed by the task manager bac k to the same tdm port via the tdm formatter and tdm interface. loopback of the emulated services is achieved by redirect ing classified packets from the packet receive blocks, back to the packet network. the packet transmit bloc ks are setup to strip the or iginal header and add a new header directing the packets back to the source. 8.3 host packet generation the control processor can generate packets directly, allowi ng it to use the network for out-of-band communications. this can be used for transmission of control data or networ k setup information, e.g., r outing information. the host interface can also be used by a local resource for network transmission of processed data. the device supports dual address dma transfers of pack ets to and from the cpu memory, using the host's own dma controller. table 22 illustra tes the maximum bandwidths achiev able by an external dma master. note 1: maximum bandwidths are the maximum the zl5011x devices can transfer under host control, and assumes only minimal packet processing by the host. note 2: combined figures assume the same amount of data is to be transferred each way. 8.4 loss of service (los) during normal transmission a situation may arise where a lo ss of service occurs, caused by a disruption in the transmission line due to engineering works or cable disc onnection for example. this results in the loss of a tdm signal, including the associated tdm clock, from the liu. with no tdm signal or clock, no packets can be assemb led by the transmitting zl5011x device, and the flow of packets will cease. the absence of packets at the receiving zl5011x device will cause underrun data to be generated at the tdm output, nor mally an ?all-ones? pattern, with the e xception of ds3 which alternates ones and zeros. the los condition is detected by the receive zl5011x device. additionally, when the liu detects los, it can notify the cpu. the cpu can set a control bit in the packet header (bit l in the ietf drafts), which is then transmitted. t he receiving zl5011x device recognizes the control bit, and transmits an ais (all-ones) pattern on the appropriate tdm stream. dma path packet size max bandwidth mbps 1 zl5011x to cpu only >1000 bytes 50 zl5011x to cpu only 60 bytes 6.7 cpu to zl5011x only >1000 bytes 60 cpu to zl5011x only 60 bytes 43 combined 2 >1000 bytes 58 (29 each way) combined 2 60 bytes 11 (5.5 each way) table 22 - dma maximum bandwidths zl50115/16/17/18/19/20 data sheet 58 zarlink semiconductor inc. using both mechanisms provides a robust method of indicating an los conditi on to the downstream tdm equipment. 8.5 power up sequence to power up the zl5011x the following procedure must be used: ? the core supply must never exceed the i/o supply by more than 0.5v dc ? both the core supply and the i/o supply must be brought up together ? the system reset and, if used, the jtag reset must remain low until at least 100 s after the 100 mhz system clock has stabilised. note that if jtag reset is not used it must be tied low this is illustrated in the diagram shown in figure 22. figure 22 - powering up the zl5011x 8.6 jtag interface and board level test features. the jtag interface is used to access the boundar y scan logic for board level production testing. 8.7 external component requirements ? direct connection to powerquicc? ii (mpc8260) host processor and associated memory, but can support other processors with appropriate glue logic ? tdm framers and/or line interface units ? ethernet phy for each mac port rst sclk v dd i/o supply (3.3 v) core supply (1.8 v) 10 ns > 100 s <0.5 v dc t t t zl50115/16/17/18/19/20 data sheet 59 zarlink semiconductor inc. 8.8 miscellaneous features ? system clock speed of 100 mhz ? host clock speed of up to 66 mhz ? debug option to freeze all internal state machines ? jtag (ieee1149) test access port ? 3.3 v i/o supply rail with 5 v tolerance ? 1.8 v core supply rail ? fully compatible with mt90880/1/2/3 and zl50110/11/14 zarlink product line 8.9 test modes operation 8.9.1 overview the zl5011x family supports the following modes of operation. 8.9.1.1 system normal mode this mode is the device's normal operating mode. boundary scan testing of the peripheral ring is accessible in this mode via the dedicated jtag pins. the jtag interface is compliant with t he ieee std. 1149.1-2001; test access port and boundary scan architecture. each variant has it's own dedicated.bsdl file wh ich fully describes it's boundary scan architecture. 8.9.1.2 system tri-state mode all output and i/o output driv ers are tri-stated allowing the device to be isolated when testing or debugging the development board. 8.9.2 test mode control the system test mode is selected using the dedicated devi ce input bus test_mode[2:0] as follows in table 23. 8.9.3 system normal mode selected by test_mode[2:0] = 3'b000. as the test_mode[2: 0] inputs have internal pull-downs this is the default mode of operation if no external pull-up/downs are connected. the gpio[15:0] bus is captured on the rising edge of the external reset to provide internal bootstrap options. after the internal reset has been de-asserted the gpio pins may be configured by the adm modul e as either inputs or outputs. 8.9.4 system tri-state mode selected by test_mode[2:0] = 3'b011. all device output and i/o output drivers are tri-stated. system test mode test_mode[2:0] sys_normal_mode 3?b000 sys_tri_state_mode 3?b011 table 23 - test mode control zl50115/16/17/18/19/20 data sheet 60 zarlink semiconductor inc. 9.0 dpll specification the zl5011x family incorporates an internal dpll t hat meets telcordia gr-1244-core stratum 3 and stratum 4/4e requirements, assuming an appropri ate clock oscillator is connected to the system clock pin. it will meet the jitter/wander tolerance, jitter/wander transfer, intrinsi c jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency and mtie requirements fo r these specifications. in structured mode with the zl5011x device operating as a master the dpll is used to provide clock and frame reference signals to the internal and external tdm infrastructure. in structured mode, with the zl5011x device operating as a slave, the dpll is not used. all tdm clock generation is perf ormed externally and the input streams are synchronised to the system clock by the tdm interface. the dpll is not required in uns tructured mode, where tdm cl ock and frame signals are generated by internal dco?s assigned to each individual stream. 9.1 modes of operation it can be set into one of four operating modes: locking mode, holdover mode, freerun mode and powerdown mode. 9.1.1 locking mo de (normal operation) the dpll accepts a reference signal from either a primar y or secondary source, providing redundancy in the event of a failure. these references should have the same nominal frequencies but do not need to be identical as long as their frequency offsets meet the appropriate stratum requ irements. each source is selected from any one of the available tdm input stream clocks (up to 4 on the zl50117/20 variants), or from the external tdm_clkip (primary) or tdm_clkis (secondary) input pins, as illustrated in fi gure 16 - on page 51. it is possible to supply a range of input frequencies as the dpll reference source, depicted in table 24. the prd register value is the number (in hexadecimal) that must be programmed into the prd register within the dpll to obtain the divided down frequency at pll_pri or pll_sec. note 1: a prd/srd value of 0 will suppress the clock, and prevent it from reaching the dpll. note 2: ui means unit interval - in this case periods of the time signal. so 1ui on a 64 khz signal means 15.625 s, the period of the reference frequency. similarly 1023ui on a 4.096 mhz signal means 250 s. note 3: this input frequency is supported with the use of an external divide by 2. source input frequency (mhz) tolerance ( ppm) divider ratio prd/srd register value (hex) (note 1) frequency at pll_pri or pll_sec (mhz) maximum acceptable input wander tolerance (ui) (note 2) 0.008 30 1 1 0.008 1 1.544 130 1 1 1.544 1023 2.048 50 1 1 2.048 1023 4.096 50 1 1 4.096 1023 8.192 50 1 1 8.192 1023 16.384 50 1 1 16.384 1023 6.312 30 1 1 6.312 1023 22.368 20 2796 aec 0.008 1 (on 64k hz) 34.368 20 537 219 0.064 1 (on 64 khz) 44.736 (note 3) 20 699 2bb 0.064 1 (on 64 khz) table 24 - dpll input reference frequencies zl50115/16/17/18/19/20 data sheet 61 zarlink semiconductor inc. the maximum lock-in range can be programmed up to 372 ppm regardless of the input frequency. the dpll will fail to lock if the source input frequency is absent, if it is not of approximately the correc t frequency or if it is too jittery. see section 9.7 for further details. limitations depend on the users programmed values, so the dpll must be programmed properly to meet stratum 3, or stratum 4/4e. the application program interface (api) software that accompanies the zl5011x family can be used to automatically set up the dpll for the appropriate standard requirement. the dpll lock-in range can be programmed using t he lock range register (see zl50115/16/17/18/19/20 programmers model document) in order to extend or reduce the capture envelope. the dpll provides bit-error-free reference switching, me eting the specification limits in the telcordia gr-1244-core standard. if stratum 3 or stratum 4/4e accuracy is not required, it is possi ble to use a more relaxed system clock tolerance. the dpll output consists of three signals; a common cl ock (comclk), a double-rate common clock (comclkx2) and a frame reference (8 khz). these are used to time the in ternal tdm interface, and hence the corresponding tdm infrastructure attached to the interface. the output cl ock options are either 2.048 mb ps (comclkx2 at 4.096 mbps) or 8.192 mbps (comclkx2 at 16.384 mbps ), determined by setup in the dpll control register. the frame pulse is programmable for polarity and width. 9.1.2 holdover mode in the event of a reference failure resulting in an absence of both the primary and secondary source, the dpll automatically reverts to holdover mode. the last valid frequency value recorded before failure can be maintained within the stratum 3 limits of 0.05 ppm. the hold va lue is wholly dependent on the drift and temperature performance of the system clock. for example, a 32 ppm oscillator may have a temperature coefficient of 0.1 ppm/c. thus a 10c ambient change since the dpll was last in the locking mode will change the holdover frequency by an additional 1 ppm, which is much greater t han the 0.05 ppm stratum 3 specification. if the strict target of stratum 3 is not required, a less rest rictive oscillator can be used for the system clock. holdover mode is typically used for a short period of time until network synchronisation is re-established. 9.1.3 freerun mode in freerun mode the dpll is programmed with a centre frequency, and can output that frequency within the stratum 3 limits of 4.6 ppm. to achieve this the 100 mhz system clock must have an absolute frequency accuracy of 4.6 ppm. the centre frequency is programmed as a fraction of the system clock frequency. 9.1.4 powerdown mode it is possible to ?power down? the dpll when it is not in use. for example, an unstructured tdm system, or use of an external dpll would mean the internal dpll could be sw itched off, saving power. the in ternal registers can still be accessed while the dpll is powered down. 9.2 reference monitor circuit there are two identical reference monitor circuits, o ne for the primary and one for the secondary source. each circuit will continually monitor its reference, and report the references validity. the validity criteria depends on the frequency programmed for the reference. a reference must meet all the following criteria to maintain validity: ? the ?period in specified range? check is performed regardless of the programmed frequency. each period must be within a range, which is programmable for th e application. refer to the zl50115/16/17/18/19/20 programmers model for details. ? if the programmed frequency is 1.544 mhz or 2.048 mhz, t he ?n periods in specified range? check will be performed. the time taken for n cycles must be within a programmed range, typically with n at 64, the time taken for consecutive cycles must be between 62 and 66 periods of the programmed frequency. zl50115/16/17/18/19/20 data sheet 62 zarlink semiconductor inc. the fail flags are independent of the preferred option for primar y or secondary operation, will be asserted in the event of an invalid signal regardless of mode. 9.3 locking mode reference switching when the reference source the dpll is currently locking to becomes invalid, the dpll?s response depends on which one of the failure detect modes has been chosen: au todetect, forced primary, or forced secondary. one of these failure detect modes must be chosen via the fdm1:0 bits of the dom register. after a device reset via the system_reset pin, the autodetect mode is selected. in autodetect mode (automatic reference switching) if both references are valid the dpll will synchronise to the preferred reference. if the preferred reference becomes unreliable, the dpll c ontinues driving its output clock in a stable holdover state until it makes a switch to the back up reference. if the preferred reference recovers, the dpll makes a switch back to the preferred reference. if nece ssary, the switch back can be prevented by changing the preferred reference using the refsel bit in the dom r egister, after the switch to the backup reference has occurred. if both references are unreliable, the dpll will drive it s output clock using the stable holdover values until one of the references becomes valid. in forced primary mode, the dpll will synchronise to the primary reference only. the dpll will not switch to the secondary reference under any circumstances including the loss of the primary reference. in this condition, the dpll remains in holdover mode until the primary refer ence recovers. similarly in forced secondary mode, the dpll will synchronise to the secondary reference only, and will not switch to the primary reference. again, a failure of the secondary reference will cause the dpll to enter ho ldover mode, until such time as the secondary reference recovers. the choice of preferred reference has no effect in these modes. when a conventional pll is locked to its reference, ther e is no phase difference between the input reference and the pll output. for the dpll, the input references can have any phase relationship between them. during a reference switch, if the dpll output follows the phase of the new reference, a large phase jump could occur. the phase jump would be transferred to the tdm outputs. the dpll?s mtie (maximum time interval error) feature preserves the continuity of the dpll output so that it appears no reference sw itch had occurred. the mtie circuit is not perfect however, and a small time interval error is still incurred per reference switch. to align the dpll output clock to the nearest edge of the selected input reference, the mtie reset bit (mrst bit in the dom register) can be used. unlike some designs, switching between references whic h are at different nominal frequencies do not require intervention such as a system reset. 9.4 locking range the locking range is the input frequency range over which the dpll must be able to pull into synchronization and to maintain the synchronization. the lock ing range is programmable up to 372 ppm. note that the locking range relates to the system clock fr equency. if the external oscillator has a tolerance of -100 ppm, and the locking range is programmed to 200 ppm, the actual locking range is the programmed value shifted by the system clock tolerance to become -300 ppm to +100 ppm. 9.5 locking time the locking time is the time it takes the synchroniser to phase lock to the input signal. phase lock occurs when the input and output signals are not changing in phase wi th respect to each other (not including jitter). locking time is very difficult to determine be cause it is affected by many factors including: ? initial input to output phase difference ? initial input to output frequency difference zl50115/16/17/18/19/20 data sheet 63 zarlink semiconductor inc. ? dpll loop filter ? dpll limiter (phase slope) although a short phase lock time is des irable, it is not always achievable due to other synchroniser requirements. for instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases locking time; and a better (smaller) phase slope performance will increase locking time . additionally, the locking time is dependent on the p_shift value. the dpll loop filter and limiter have been optimised to meet the telcordia gr-1244-core jitter transfer and phase alignment speed requirements. the phase lock ti me is guaranteed to be no greater than 30 seconds when using the recommended stratum 3 and stratum 4/4e register settings. 9.6 lock status the dpll has a lock status indicator and a corresp onding lock change interrupt. the response of the lock status indicator is a function of the programmed lock dete ct interval (ldi) and lock detect threshold (ldt) values in the dpll_ldetect register. the ldt re gister can be programmed to set the ji tter tolerance level of the lock status indicator. to determine if the dpll has ac hieved lock the lock status indicator must be high for a period of at least 30 seconds. when the dpll loses lock the lock status indicator will go low after ldi x 125 s. 9.7 jitter the dpll is designed to withstand, and improv e inherent jitter in the tdm clock domain. 9.7.1 acceptance of input wander for t1(1.544 mhz), e1(2.048 mhz) and j2(6.312 mhz) input frequencies, the dpll will accept a wander of up to 1023ui pp at 0.1 hz to conform with the relevant specificati ons. for the 8 khz (frame rate) and 64 khz (the divided down output for t3/e3) input frequencie s, the wander acceptance is limited to 1 ui (0.1 hz). this principle is illustrated in table 24. 9.7.2 intrinsic jitter intrinsic jitter is the jitter produced by a synchronizer and measured at its output. it is measured by applying a jitter free reference signal to the input of the device, and measur ing its output jitter. intrinsic jitter may also be measured when the device is in a non synchronizing mode such as free running or holdover, by me asuring the output jitter of the device. intrinsic jitter is usually measured with various band-limiting filters, depending on the applicable standards. the intrinsic jitter in the dpll is reduced to less than 1 ns p-p 1 by an internal tapped delay line (tdl). the dpll can be programmed so that the output clock meets all the stratum 3 requirements of telcordia gr-1244-core. stratum 4/4e is also supported. 9.7.3 jitter tolerance jitter tolerance is a measure of the ability of a pll to oper ate properly without cycle slips (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. the applied jitter magnitude and the ji tter frequency depends on the applicable standards. the dpll?s jitter tolerance can be programmed to m eet telcordia gr-1244-core ds1 reference input jitter tolerance requirements. 1. there are 2 exceptions to this. a) when reference is 8 khz, and reference frequency offset relative to the master is small, j itter up to 1 master clock period is possible, i.e. 10 ns p-p. b) in holdover mode, if a huge amount of jitter had been present prior to entering hol dover, then an additional 2 ns p-p is possible. zl50115/16/17/18/19/20 data sheet 64 zarlink semiconductor inc. 9.7.4 jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. i nput jitter is applied at va rious amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. since intrinsic jitter is always presen t, jitter attenuation will appear to be lo wer for small input jitter signals than larger ones. consequently, accurate jitter transfer functi on measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). the internal dpll is a first order type 2 component, so a fr equency offset doesn?t result in a phase offset. stratum 3 requires a -3 db frequency of less than 3 hz. the nature of the filter results in some peaking, resulting in a -3 db frequency of 1.9 hz and a 0.08 db peak with a system cl ock frequency of 100 mhz assuming a p_shift value of 2. the transfer function is illustrated in figure 24 and in more detail in figure 25. increasing the p_shift value increases the speed the dpll will lock to the required frequency and reduces the peak, but also reduces the tolerance to jitter - so the p_shift value must be progra mmed correctly to meet stratum 3 or stratum 4/4e jitter transfer characteristics. this is done automatically in the api. 9.8 maximum time interval error (mtie) in order to meet several standards requirements, the phase shift of the dpll output must be controlled. a potential phase shift occurs every time the dpll is re-arranged by changing reference source signal, or the mode. in order to meet the requirements of stratum 3, the dpll will shift phase by no more than 20 ns per re-arrangement. additionally the speed at which the change occurs is al so critical. a large step change in output frequency is undesirable. the rate of change is programmable using t he skew register, up to a maximum of 15.4 ns / 125 s (124 ppm). figure 23 - jitter transfer function zl50115/16/17/18/19/20 data sheet 65 zarlink semiconductor inc. figure 24 - jitter transfer function - detail 10.0 memory map an d register definitions all memory map and register def initions are included in the z l50115/16/17/18/19/20 pr ogrammers model document. 11.0 dc characteristics * exceeding these figures may cause permanent damage. functional operation under these conditions is not guaranteed. voltage measurements are with respect to ground (v ss ) unless otherwise stated. * the core and pll supply voltages must never be allowed to exceed the i/o supply voltage by more than 0.5 v during power-up. fa ilure to observe this rule could lead to a high-current latch-up state, po ssibly leading to chip failure, if sufficient cross-supply cur rent is available. to be safe ensure the i/o supply voltage supply always rises earlier than the core and pll supply voltages. absolute maximum ratings* parameter symbol min. max. units i/o supply voltage v dd_io -0.5 5.0 v core supply voltage v dd_core -0.5 2.5 v pll supply voltage v dd_pll -0.5 2.5 v input voltage v i -0.5 v dd + 0.5 v input voltage (5 v tolerant inputs) v i_5v -0.5 7.0 v continuous current at digital inputs i in - 10 ma continuous current at digital outputs i o - 15 ma package power dissipation pd - 2.38 w storage temperature ts -55 +125 c zl50115/16/17/18/19/20 data sheet 66 zarlink semiconductor inc. typical figures are at 25 c and are for design aid only, they are not guaranteed and not subject to production testing. voltage measurements are with respect to ground (v ss ) unless otherwise stated. recommended operating conditions characteristics symbol min. typ. max. units test condition operating temperature t op -40 25 +85 c junction temperature t j -40 - 125 c positive supply voltage, i/o v dd_io 3.0 3.3 3.6 v positive supply voltage, core v dd_core 1.65 1.8 1.95 v positive supply voltage, core v dd_pll 1.65 1.8 1.95 v input voltage low - all inputs v il --0.8v input voltage high v ih 2.0 - v dd_io v input voltage high, 5 v tolerant inputs v ih_5v 2.0 - 5.5 v zl50115/16/17/18/19/20 data sheet 67 zarlink semiconductor inc. dc electrical ch aracteristics - t ypical characteristics are at 1.8 v core, 3.3 v i/o, 25 c and typical processing. the min. and max. values are defined over all process conditions, from -40 to 125 c junction temperature, core voltage 1.65 to 1.95 v and i/o voltage 3.0 and 3.6 v unless otherwise stated. note 1: the io and core supply current worst case figures apply to different scenarios and can not simply be summed for a total figure. for a clearer indication of power consumption, please refer to section 13.0. note 2: worst case assumes the maximum number of active contexts and channels. figures are for the ZL50120. for an indication of typical power consumption, please refer to section 13.0. characteristics symbol min. typ. max. units. test condition input leakage i leip 1 a no pull up/down v dd_io = 3.6 v output (high impedance) leakage i leop 2 a no pull up/down v dd_io = 3.6 v input capacitance c ip 1pf output capacitance c op 4pf pullup current i pu -27 a input at 0 v pullup current, 5 v tolerant inputs i pu_5v -110 a input at 0 v pulldown current i pd 27 a input at v dd_io pulldown current, 5 v tolerant inputs i pd_5v 110 a input at v dd_io core 1.8 v supply current i dd_core 950 ma note 1,2 pll 1.8 v supply current i dd_pll 1.30 ma i/o 3.3 v supply current i dd_io 120 ma note 1,2 input levels characteristics symbol min. typ. max. units test condition input low voltage v il 0.8 v input high voltage v ih 2.0 v positive schmitt threshold v t+ 1.6 v negative schmitt threshold v t- 1.2 v output levels characteristics symbol min. typ. max. units test condition output low voltage v ol 0.4 v i ol = 6 ma. i ol = 12 ma for packet interface (m*) pins and gpio pins. i ol = 24 ma for led pins. output high voltage v oh 2.4 v i oh = 6 ma. i oh = 12 ma for packet interface (m*) pins and gpio pins. i oh = 24 ma for led pins. zl50115/16/17/18/19/20 data sheet 68 zarlink semiconductor inc. 12.0 ac characteristics 12.1 tdm interface timing - st-bus the tdm bus either operates in slave mode, where the tdm clocks for each stream are provided by the device sourcing the data, or master mode, where the tdm clocks are generated from the zl5011x. 12.1.1 st-bus slave clock mode tdm st-bus slave timing specification data format parameter symbol min. typ. max. units notes st-bus 8.192 mbps mode tdm_clki period t c16ip 54 60 66 ns tdm_clki high t c16ih 27 - 33 ns tdm_clki low t c16il 27 - 33 ns st-bus 2.048 mbps mode tdm_clki period t c4ip - 244.1 - ns tdm_clki high t c4ih 110 - 134 ns tdm_clki low t c4il 110 - 134 ns all modes tdm_f0i width 8.192 mbps 2.048 mbps t foiw 50 200 - - - 300 ns tdm_f0i setup time t fois 5 - - ns with respect to tdm_clki falling edge tdm_f0i hold time t foih 5 - - ns with respect to tdm_clki falling edge tdm_sto delay t stod 1 - 20 ns with respect to tdm_clki load c l = 50 pf tdm_sti setup time t stis 5 - - ns with respect to tdm_clki tdm_sti hold time t stih 5 - - ns with respect to tdm_clki zl50115/16/17/18/19/20 data sheet 69 zarlink semiconductor inc. in synchronous mode the clock must be within the locki ng range of the dpll to functi on correctly ( 245 ppm). in asynchronous mode, the clock may be any frequency. figure 25 - tdm st-bus slave mode timing at 8.192 mbps figure 26 - tdm st-bus slave mode timing at 2.048 mbps channel 127 bit 1 channel 127 bit 0 channel 0 bit 7 channel 0 bit 6 ch0 bit7 channel 127 bit 1 channel 127 bit 0 channel 0 bit 7 t stod t stod t stod t stih t stis t stih t stis t stih t stis t foih t fois t c16ip tdm_ckli tdm_f0i tdm_sti tdm_sto channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 ch 31 bit 0 ch 0 bit 7 ch 0 bit 6 t stod t stod t foih t fois t stih t stis t foiw t c4ip t c2ip tdm_clki (2.048 mhz) tdm_clki (4.096 mhz) tdm_f0i tdm_sti tdm_sto zl50115/16/17/18/19/20 data sheet 70 zarlink semiconductor inc. 12.1.2 st-bus master clock mode figure 27 - tdm bus master mode timing at 8.192 mbps data format parameter symbol min. typ. max. units notes st-bus 8.192 mbps mode tdm_clko period t c16op 54.0 61.0 68.0 ns tdm_clko high t c16oh 23.0 - 37.0 ns tdm_clko low t c16ol 23.0 - 37.0 ns st-bus 2.048 mbps mode tdm_clko period t c4op 237.0 244.1 251.0 ns tdm_clko high t c4oh 115.0 - 129.0 ns tdm_clko low t c4ol 115.0 - 129.0 ns all modes tdm_f0o delay t fod - - 25 ns with respect to tdm_clko falling edge tdm_sto delay active-active t stod - - 5 ns with respect to tdm_clko falling edge tdm_sto delay active to hiz and hiz to active t dz , t zd - - 33 ns with respect to tdm_clko falling edge tdm_sti setup time t stis 5 - - ns with respect to tdm_clko tdm_sti hold time t stih 5 - - ns with respect to tdm_clko table 25 - tdm st-bus master timing specification channel 127 bit 0 channel 0 bit 7 channel 0 bit 6 b0 b7 b6 ch 127 bit 0 ch 0 bit 7 ch 0 bit 6 t stod t stod t fod t fod t stih t stis t stih t stis t c16op tdm_clko tdm_f0o tdm_sti tdm_sto zl50115/16/17/18/19/20 data sheet 71 zarlink semiconductor inc. figure 28 - tdm bus master mode timing at 2.048 mbps 12.2 tdm interface timing - h.110 mode these parameters are based on the h.110 specification from the enterprise computer telephony forum (ectf) 1997. note 1: tdm_c8 and tdm_frame signals are required to meet the same timing standards and so are not defined independently. note 2: tdm_c8 corresponds to pin tdm_clki. note 3: t doz and t zdo apply at every time-slot boundary. note 4: refer to h.110 standard from enterprise computer telephony forum (ectf) for the source of these numbers. note 5: the tdm_frame signal is centred on the rising edge of tdm_c8. a ll timing measurements are based on this rising edge point; tdm_frame corresponds to pin tdm_f0i. note 6: phase correction ( ) results from dpll timing corrections. parameter symbol min. typ. max. units notes tdm_c8 period t c8p 122.066- 122 122.074+ ns note 1 note 2 tdm_c8 high t c8h 63- - 69+ ns tdm_c8 low t c8l 63- - 69+ ns tdm_d output delay t dod 0 - 11 ns load - 12 pf tdm_d output to hiz t doz - - 33 ns load - 12 pf note 3 tdm_d hiz to output t zdo 0 - 11 ns load - 12 pf note 3 tdm_d input delay to valid t dv 0-83nsnote 4 tdm_d input delay to invalid t div 102 - 112 ns note 4 tdm_frame width t fp 90 122 180 ns note 5 tdm_frame setup t fs 45 - 90 ns tdm_frame hold t fh 45 - 90 ns phase correction f 0 - 10 ns note 6 table 26 - tdm h.110 timing specification channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 ch 31 bit 0 ch 0 bit 7 ch 0 bit 6 t stod t stod t fod t fod t stih t stis t c4op t c2op tdm_clko (2.048 mhz) tdm_clko (4.096 mhz) tdm_f0o tdm_sti tdm_sto zl50115/16/17/18/19/20 data sheet 72 zarlink semiconductor inc. figure 29 - h.110 timing diagram 12.3 tdm interface timing - h-mvip these parameters are based on the multi-vendor integrat ion protocol (mvip) specification for an h-mvip bus, release 1.1a (1997). positive transitions of tdm_c2 are sync hronous with the falling edges of tdm_c4 and tdm_c16 . the signals tdm_c2, tdm_c4 and tdm_c16 correspond with pins tdm_clki. the signals tdm_f0 correspond with pins tdm_f0i . the signals tdm_hds correspond with pins tdm_sti and tdm_sto. parameter symbol min. typ. max. units notes tdm_c2 period t c2p 487.8 488.3 488.8 ns tdm_c2 high t c2h 220 - 268 ns tdm_c2 low t c2l 220 - 268 ns tdm_c4 period t c4p 243.9 244.1 244.4 ns tdm_c4 high t c4h 110 - 134 ns tdm_c4 low t c4l 110 - 134 ns tdm_c16 period t c16p 60.9 61.0 61.1 ns tdm_c16 high t c16h 30 - 31 ns tdm_c16 low t c16l 30 - 31 ns tdm_hds output delay t pd - - 30 ns at 8.192 mbps tdm_hds output delay t pd - - 100 ns at 2.048 mbps tdm_hds output to hiz t hzd --30ns tdm_hds input setup t s 30 - 0 ns tdm_hds input hold t h 30 - 0 ns tdm_f0 width t fw 200 244 300 ns table 27 - tdm h-mvip timing specification t c8p ts 127 bit 8 ts 0 bit 1 ts 0 bit 2 ts 127 bit 8 ts 0 bit 1 ts 0 bit 2 t dod t zdo t doz t div t dv t t fh t fp t fs t c8l t c8h tdm_c8 tdm_frame tdm_d input tdm_d output zl50115/16/17/18/19/20 data sheet 73 zarlink semiconductor inc. figure 30 - tdm - h-mvip timing di agram for 16 mhz clock (8.192 mbps) tdm_f0 setup t fs 50 - 150 ns tdm_f0 hold t fh 50 - 150 ns parameter symbol min. typ. max. units notes table 27 - tdm h-mvip timing specification (continued) t c16p ts 127 bit 7 ts 0 bit 0 ts 0 bit 1 ch 127 bit 7 ch 0 bit 0 t pd t hzd t h t s t fh t fs t fw t t c16h t t c16l tdm_c16 tdm_f0 tdm_hds input tdm_hds output zl50115/16/17/18/19/20 data sheet 74 zarlink semiconductor inc. 12.4 tdm liu interface timing the tdm interface can be used to directly drive into a line interface unit (liu). the interface can work in this mode with e1, ds1, j2, e3 and ds3. the frame pulse is not present, just data and clock is transmitted and received. table 28 shows timing for ds3, which woul d be the most stri ngent requirement. figure 31 - tdm-liu structured transmission/reception parameter symbol min. typ. max. units notes tdm_txclk period t ctp 22.353 ns ds3 clock tdm_txclk high t cth 6.7 ns tdm_txclk low t ctl 6.7 ns tdm_rxclk period t crp 22.353 ns ds3 clock tdm_rxclk high t crh 9.0 ns tdm_rxclk low t crl 9.0 ns tdm_txdata output delay t pd 3-10ns tdm_rxdata input setup t s 6ns tdm_rxdata input hold t h 3ns table 28 - tdm - liu structured transmission/reception t pd t h t s t crl t crp t crh t ctl t ctp t cth tdm_txclk tdm_txdata tdm_rxclk tdm_rxdata zl50115/16/17/18/19/20 data sheet 75 zarlink semiconductor inc. 12.5 pac interface timing 12.6 packet interface timing data for the mii/gmii/tbi packet switching is based on specification ieee std. 802.3 - 2000. 12.6.1 mii transmit timing parameter symbol min. typ. max. units notes tdm_clkip high / low pulsewidth t cpp 10 - - ns tdm_clkis high / low pulsewidth t csp 10 - - ns table 29 - pac timing specification parameter symbol 100 mbps units notes min. typ. max. txclk period t cc -40-ns txclk high time t chi 14 - 26 ns txclk low time t clo 14 - 26 ns txclk rise time t cr --5ns txclk fall time t cf --5ns txclk rise to txd[3:0] active delay (txclk rising edge) t dv 1 - 25 ns load = 25 pf txclk to txen active delay (txclk rising edge) t ev 1 - 25 ns load = 25 pf txclk to txer active delay (txclk rising edge) t er 1 - 25 ns load = 25 pf table 30 - mii transmit timing - 100 mbps zl50115/16/17/18/19/20 data sheet 76 zarlink semiconductor inc. figure 32 - mii transmit timing diagram 12.6.2 mii receive timing parameter symbol 100 mbps units notes min. typ. max. rxclk period t cc -40-ns rxclk high wide time t ch 14 20 26 ns rxclk low wide time t cl 14 20 26 ns rxclk rise time t cr --5ns rxclk fall time t cf --5ns rxd[3:0] setup time (rxclk rising edge) t ds 10 - - ns rxd[3:0] hold time (rxclk rising edge) t dh 5- -ns rxdv input setup time (rxclk rising edge) t dvs 10 - - ns rxdv input hold time (rxclk rising edge) t dvh 5- -ns rxer input setup time (rxcl edge) t ers 10 - - ns rxer input hold time (rxclk rising edge) t erh 5- -ns table 31 - mii receive timing - 100 mbps t dv t ev t ev t er t er t ch t cl t cc txclk txen txd[3:0] txer zl50115/16/17/18/19/20 data sheet 77 zarlink semiconductor inc. figure 33 - mii receive timing diagram t dh t ds t dvh t dvs t erh t ers t chi t clo t cc rxclk rxdv rxd[3:0] rxer zl50115/16/17/18/19/20 data sheet 78 zarlink semiconductor inc. 12.6.3 gmii transmit timing figure 34 - gmii transmit timing diagram parameter symbol 1000 mbps units notes min. typ. max. gtxclk period t gc 7.5 - 8.5 ns gtxclk high time t gch 2.5 - - ns gtxclk low time t gcl 2.5 - - ns gtxclk rise time t gcr --1ns gtxclk fall time t gcf --1ns gtxclk rise to txd[7:0] active delay t dv 1.5 - 6 ns load = 25 pf gtxclk rise to txen active delay t ev 2-6ns load = 25 pf gtxclk rise to txer active delay t er 1-6ns load = 25 pf table 32 - gmii transmit timing - 1000 mbps t dv t ev t ev t er t er t ch t cl t cc gtxclk txen txd[3:0] txer zl50115/16/17/18/19/20 data sheet 79 zarlink semiconductor inc. 12.6.4 gmii receive timing figure 35 - gmii receive timing diagram parameter symbol 1000 mbps units notes min. typ. max. rxclk period t cc 7.5 - 8.5 ns rxclk high wide time t ch 2.5 - - ns rxclk low wide time t cl 2.5 - - ns rxclk rise time t cr --1ns rxclk fall time t cf --1ns rxd[7:0] setup time (rxclk rising edge) t ds 2- -ns rxd[7:0] hold time (rxclk rising edge) t dh 1- -ns rxdv setup time (rxclk rising edge) t dvs 2- -ns rxdv hold time (rxclk rising edge) t dvh 1- -ns rxer setup time (rxclk rising edge) t ers 2- -ns rxer hold time (rxclk rising edge) t erh 1- -ns table 33 - gmii receive timing - 1000 mbps t dh t ds t dvh t dvs t erh t ers t chi t clo t cc rxclk rxdv rxd[7:0] rxer zl50115/16/17/18/19/20 data sheet 80 zarlink semiconductor inc. 12.6.5 tbi interface timing figure 36 - tbi transmit timing diagram parameter symbol 1000 mbps units notes min. typ. max. gtxclk period t gc 7.5 - 8.5 ns gtxclk high wide time t gh 2.5 - - ns gtxclk low wide time t gl 2.5 - - ns txd[9:0] output delay (gtxclk rising edge) t dv 1 - 6 load = 25 pf rcb0/rbc1 period t rc 15 16 17 ns rcb0/rbc1 high wide time t rh 5- -ns rcb0/rbc1 low wide time t rl 5- -ns rcb0/rbc1 rise time t rr --2ns rcb0/rbc1 fall time t rf --2ns rxd[9:0] setup time (rcb0 rising edge) t ds 2- -ns rxd[9:0] hold time (rcb0 rising edge) t dh 1- -ns refclk period t fc 7.5 - 8.5 ns refclk high wide time t fh 2.5 - - ns refclk low wide time t fl 2.5 - - ns table 34 - tbi timing - 1000 mbps /i/ /s/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /t/ /r/ /i/ t dv t gc gtxclk txd[9:0] signal_detect zl50115/16/17/18/19/20 data sheet 81 zarlink semiconductor inc. figure 37 - tbi receive timing diagram 12.6.6 management interface timing the management interface is common for all inputs and consists of a serial data i/o line and a clock line. note 1: refer to clause 22 in ieee8 02.3 (2000) standard for input/out put signal timing characteristics. note 2: refer to clause 22c.4 in ieee802.3 (2000) standard for output load description of mdio. figure 38 - management interface timing for ethernet port - read figure 39 - management interface timing for ethernet port - write parameter symbol min. typ. max. units notes m_mdc clock output period t mp 1990 2000 2010 ns note 1 m_mdc high t mhi 900 1000 1100 ns m_mdc low t mlo 900 1000 1100 ns m_mdc rise time tmr - - 5 ns m_mdc fall time t mf --5ns m_mdio setup time (mdc rising edge) t ms 10 - - ns note 1 m_mdio hold time (m_mdc rising edge) t mh 10 - - ns note 1 m_mdio output delay (m_mdc rising edge) t md 1 - 300 ns note 2 table 35 - mac management timing specification /i/ /s/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /t/ /r/ /i/ t dh t ds t dh t ds t rc t rc rbc1 rbc0 rxd[9:0] signal_detect t mh t ms t mlo t mhi m_mdc m_mdio t md t mp m_mdc m_mdio zl50115/16/17/18/19/20 data sheet 82 zarlink semiconductor inc. 12.7 cpu interface timing note 1: load = 50 pf maximum note 2: the maximum value of t ctv may cause setup violations if directly connected to the mpc8260. see section 14.2 for details of how to accommodate this during board design. parameter symbol min. typ. max. units notes cpu_clk period t cc 15.152 ns cpu_clk high time t cch 6ns cpu_clk low time t ccl 6ns cpu_clk rise time t ccr 4ns cpu_clk fall time t ccf 4ns cpu_addr[23:2] setup time t cas 4ns cpu_addr[23:2] hold time t cah 2ns cpu_data[31:0] setup time t cds 4ns cpu_data[31:0] hold time t cdh 2ns cpu_cs setup time t css 4ns cpu_cs hold time t csh 2ns cpu_we /cpu_oe setup time t ces 5ns cpu_we /cpu_oe hold time t ceh 2ns cpu_ts _ale setup time t cts 4ns cpu_ts _ale hold time t cth 2ns cpu_sdack1 /cpu_sdack2 setup time t cks 2ns cpu_sdack1 /cpu_sdack2 hold time t ckh 2nsnote 1 cpu_ta output valid delay t ctv 2 11.3 ns note 1, 2 cpu_dreq0 /cpu_dreq1 output valid delay t cwv 26nsnote 1 cpu_ireq0 /cpu_ireq1 output valid delay t crv 26nsnote 1 cpu_data[31:0] output valid delay t cdv 27nsnote 1 cpu_cs to output data valid t sdv 3.2 10.4 ns cpu_oe to output data valid t odv 3.3 10.4 ns cpu_clk(falling) to cpu_ta valid t otv 3.2 9.5 ns table 36 - cpu timing specification zl50115/16/17/18/19/20 data sheet 83 zarlink semiconductor inc. the actual point where read/write data is transferred occurs at the positive clock edge following the assertion of cpu_ta , not at the positive clock edge during the assertion of cpu_ta . figure 40 - cpu read - mpc8260 figure 41 - cpu write - mpc8260 t otv t ctv t ctv t otv t sdv t odv t cdv t sdv t odv t cth t cts t ceh t ces t csh t css t cah t cas 0 or more cycles 0 or more cycles t cc note: cpu_data is valid when cpu_ta is asserted. cpu_data will re main valid while both cpu_cs and cpu_oe are asserted. cpu_ta will continue to be driven until cpu_cs is deasserted. cpu_clk cpu_addr[23:2] cpu_cs cpu_oe cpu_we cpu_ts _ale cpu_data[31:0] cpu_ta cpu_cs and cpu_oe must both be asserted to enable the cpu_data output. t otv t ctv t ctv t otv t cdh t cds t cth t cts t ceh t ces t csh t css t cah t cas 0 or more cycles 0 or more cycles t cc 0 or more cycles 0 or more cycles note: following assertion of cpu_ta, cpu_cs may be deasserted. the mpc8260 will continue to assert cpu_cs until cpu_ta has been synchronized internally. cpu_ ta will continue to be driven until cpu_cs is finally deasserted. during continued assertion of cpu_cs, cpu_we and cpu_data may be removed. cpu_clk cpu_addr[23:2] cpu_cs cpu_oe cpu_we cpu_ts_ale cpu_data[31:0] cpu_ta zl50115/16/17/18/19/20 data sheet 84 zarlink semiconductor inc. figure 42 - cpu dma read - mpc8260 figure 43 - cpu dma write - mpc8260 t otv t ctv t ctv t otv t sdv t odv t cdv t sdv t odv t cwv t cwv t cth t cts t ceh t ces t csh t css t ckh t cks 0 or more cycles 0 or more cycles t cc note 1: cpu_sdack2 must be asserted during the cycle shown. it may then be deasserted at any time. cpu_data is valid when cpu_ta is asserted (always timed as shown) . cpu_data will remain valid while cpu_cs and cpu_oe are asserted. cpu_ta will continue to be driven until cpu_cs is deasserted. cpu_cs and cpu_oe must both be asserted to enable cpu_clk cpu_dreq1 cpu_sdack2 cpu_cs cpu_oe cpu_we cpu_ts _ale cpu_data[31:0] cpu_ta the cpu_data output. note 2: cpu_dreq1 shown with postive polarity cpu_sdack2 shown with negative polarity t otv t ctv t ctv t otv t cwv t cwv t cdh t cds t cth t cts t ceh t ces t csh t css t ckh t cks 0 or more cycles 0 or more cycles t cc note 1: cpu_sdack1 must be asserted during the cycle shown. it may then be deasserted at any time. following assertion of cpu_ta (always timed as shown), cpu_cs may be deasserted. the mpc8260 will continue to assert cpu_cs until cpu_ta has been synchronized internally. cpu_ta will continue to be driven until cpu_cs is finally deasserted. during continued assertion of cpu_cs , cpu_we and cpu_data may be removed. cpu_clk cpu_dreq0 cpu_sdack1 cpu_cs cpu_oe cpu_we cpu_ts _ale cpu_data[31:0] cpu_ta note 2: cpu_dreq0 shown with positive polarity cpu_sdack1 shown with negative polarity zl50115/16/17/18/19/20 data sheet 85 zarlink semiconductor inc. 12.8 system function port note 1: the system clock frequency stability affects the holdover-ope rating mode of the dpll. holdover mode is typically used fo r a short duration while network synchronisation is temporarily disr upted. drift on the system clock directly affects the holdover mode accuracy. note that the absolute system clock accu racy does not affect the holdover accuracy, only the change in the system clock (system_clk) accuracy while in holdover. for example, if the syst em clock oscillator has a temperature coefficient of 0.1 ppm/oc, a 10oc change in temperature while the dpll is in will result in a frequency accuracy offset of 1 ppm. the intrinsic frequency accuracy of the dpll holdover mode is 0.06 ppm, excluding the system clock drift. note 2: the system clock frequency affects the operation of the dpll in free-run mode. in this mode, the dpll provides timing an d synchronisation signals which are based on the frequency of the ac curacy of the master clock (i.e., frequency of clock output equals 8.192 mhz system_c lk accuracy 0.005 ppm). note 3: the absolute system_clk accuracy must be contro lled to 30 ppm in sync hronous master mode to enable the internal dpll to function correctly. note 4: in asynchronous mo de and in synchronous sl ave mode the dpll is not used. ther efore the tolerance on system_clk may be relaxed slightly. parameter symbol min. typ. max. units notes system_clk frequency clk fr - 100 - mhz note 1 and note 2 system_clk accuracy (synchronous master mode) clk acs - - 30 ppm note 3 system_clk accuracy (synchronous slave mode and asynchronous mode) clk aca - - 200 ppm note 4 table 37 - system clock timing zl50115/16/17/18/19/20 data sheet 86 zarlink semiconductor inc. 12.9 jtag interface timing note 1: jtag_trst is an asynchronous signal. the setup time is for test purposes only. note 2: non test (other than jtag_tdi and jtag_tms ) signal input timing wi th respect to jtag_clk. note 3: non test (other than jtag_tdo) signal output with respect to jtag_clk. figure 44 - jtag signal timing parameter symbol min. typ. max. units notes jtag_clk period t jcp 40 100 ns jtag_clk clock pulse width t low, t high 20 - - ns jtag_clk rise and fall time t jrf 0-3ns jtag_trst setup time t rstsu 10 - - ns with respect to jtag_clk falling edge. note 1 jtag_trst assert time t rst 10 - - ns input data setup time t jsu 5- -nsnote 2 input data hold time t jh 15 - - ns note 2 jtag_clk to output data valid t jdv 0 - 20 ns note 3 jtag_clk to output data high impedance t jz 0 - 20 ns note 3 jtag_tms, jtag_tdi setup time t tpsu 5- -ns jtag_tms, jtag_tdi hold time t tph 15 - - ns jtag_tdo delay t topdv 0 - 15 ns jtag_tdo delay to high impedance t tpz 0 - 15 ns table 38 - jtag interface timing don't care dc hiz hiz t tpz t topdv t tph t tpsu t tph t tpsu t jcp t low t high jtag_tck jtag_tms jtag_tdi jtag_tdo zl50115/16/17/18/19/20 data sheet 87 zarlink semiconductor inc. figure 45 - jtag clock and reset timing 13.0 power characteristics the following graph in figure 47 illustrates typical power consumption figures for the zl5011x family. typical characteristics are at 1.8 v core, 3.3v i/o, 25 c and typical processing. figure 46 - zl50115/16/17/18 /19/20 power consumption plot t rstsu t rst t high t low jtag_tck jtag_trst zl50118/19/20 power consumption (typical conditions) 1.350 1.360 1.370 1.380 1.390 1.400 1.410 1234 number of active e1 unstructured contexts power (w) zl50115/16/17/18/19/20 data sheet 88 zarlink semiconductor inc. 14.0 design and layout guidelines this guide will provide information and guidance for pcb layouts when using the zl5011x. specific areas of guidance are: ? high speed clock and data, outputs and inputs ? cpu_ta output 14.1 high speed clock & data interfaces on the zl5011x series of devices t here are four high-speed da ta interfaces that need co nsideration when laying out a pcb to ensure correct termination of traces and th e reduction of crosstalk noi se. the interfaces being: ? gmac interfaces ? tdm interface ? cpu interface it is recommended that the outputs are su itably terminated using a series termin ation through a resistor as close to the output pin as possible. t he purpose of the series termination resistor is to reduce reflections on the line. the value of the series termination and the length of trace t he output can drive will depend on the driver output impedance, the characteristic impedance of the pcb trace (recommend 50 ohm), the distributed trace capacitance and the load capacitance. as a general ru le of thumb, if the trac e length is less than 1/6th of the equivalent length of the rise and fall times, then a seri es termination may not be required. the equivalent length of rise time = rise time (ps) / delay (ps/mm) for example: typical fr4 board delay = 6.8 ps/mm typical rise/fall time for a zl5011x output = 2.5 ns critical track length = (1/6) x (2500/6.8) = 61 mm therefore tracks longer than 61 mm will require termination. as a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces, this is crosstalk. if the crosstalk is of sufficiently strong ampl itude, false data can be induced in the trace and therefore it should be minimized in the layout. the voltage that the extern al fields cause is proportional to the strength of the field and the length of the tr ace exposed to the field. therefore to mini mize the effect of crosstalk some basic guidelines should be followed. first, increase separation of sensitive signals, a rough ru le of thumb is that doubling the separation reduces the coupling by a factor of four. alternativ ely, shield the victim traces from the aggressor by either routing on another layer separated by a power plane (in a correctly decouple d design the power planes have the same ac potential) or by placing guard traces between the signals usually held ground potential. particular effort should be made to mi nimize crosstalk from zl5011x outputs and ensuring fast rise time to these inputs. zl50115/16/17/18/19/20 data sheet 89 zarlink semiconductor inc. in summary: ? place series termination resistors as close to the pins as possible ? minimize output capacitance ? keep common interface traces close to the same length to avoid skew ? protect input clocks and signals from crosstalk 14.1.1 gmac interface - special considerations during layout the gmii interface passes data to and from the zl5011 x with their related transmit and receive clocks. it is therefore recommended that the trace lengths for transmit related signals and their clock and the receive related signals and their clock are kept to the same length. by doing this the ske w between individual signals and their related clock will be minimized. 14.1.2 tdm interface - special considerations during layout although the data rate of this interface is low the out puts edge speeds share the charac teristics of the higher data rate outputs and therefore must be treated with the same care extended to the other interfaces with particular reference to the lower stream numbers which support the higher data rates. the tdm interface has numerous clocking schemes and as a result of th is the input clock traces to the zl501 1x devices should be treated with care. 14.1.3 summary particular effort should be made to mi nimize crosstalk from zl5011x outputs and ensuring fast rise time to these inputs. in summary: ? place series termination resistors as close to the pins as possible ? minimize output capacitance ? keep common interface traces close to the same length to avoid skew ? protect input clocks and signals from crosstalk zl50115/16/17/18/19/20 data sheet 90 zarlink semiconductor inc. 14.2 cpu ta output the cpu_ta output signal from the zl5011x is a critic al handshake signal to the cpu that ensures the correct completion of a bus transaction between the two devices. as the signal is critic al, it is recommend that the circuit shown in figure 47 is implemented in systems operat ing above 40 mhz bus frequency to ensure robust operation under all conditions. the following external logic is required to implement the circuit: ? 74lcx74 dual d-type flip-flop (one section of two) ? 74lcx08 quad and gate (one section of four) ? 74lcx125 quad tri-state buffer (one section of four) ? 4k7 resistor x2 figure 47 - cpu_ta board circuit the function of the circuit is to extend the ta signal, to ensure the cpu corr ectly registers it. resistor r2 must be fitted to ensure correct operati on of the ta input to the processor. it is recommended that the logic is fitted close to the zl5011x and that the clock to the 74lcx74 is derived from the same clock source as that input to the zl5011x. d q cpu_clk cpu_ta from zl5011x cpu_cs to zl5011x to zl5011x + 3v3 +3v3 cpu_ta to cpu r1 r2 4k7 4k7 zl50115/16/17/18/19/20 data sheet 91 zarlink semiconductor inc. 15.0 reference documents 15.1 external standards/specifications ? ieee standard 1149.1-2001; test access port and boundary scan architecture ? ieee standard 802.3-2000; local and metropolitan networks csma/cd access method and physical layer ? ectf h.110 revision 1.0; hardware compatibility specification ? h-mvip (go-mvip) standard release 1.1a; multi-vendor integration protocol ? mpc8260aec/d revision 0.7; motorola mpc8260 family hardware specification ? rfc 768; udp ? rfc 791; ipv4 ? rfc2460; ipv6 ? rfc 1889; rtp ? rfc 2661; l2tp ? rfc 1213; mib ii ? rfc 1757; remote network monitoring mib (for smiv1) ? rfc 2819; remote network monitoring mib (for smiv2) ? rfc 2863; interfaces group mib ? ccitt g.712; tdm timing specification (method 2) ? g.823; control of jitter/wander with digita l networks based on the 2.048 mbps hierarchy ? g.824; control of jitter/wander with digita l networks based on the 1.544 mbps hierarchy ? ansi t1.101 stratum 3/4 ? telcordia gr-1244-core stratum 3/4/4e ? ietf pwe3 draft-ietf-l2tpext-l2tp-base-02 ? ietf pwe3 draft-ietf-pwe3-cesopsn ? ietf pwe3 draft-ietf-pwe3-satop ? itu-t y.1413 tdm-mpls network interworking 15.2 zarlink standards ? msan-126 revision b, issue 4; st- bus generic device specification zl50115/16/17/18/19/20 data sheet 92 zarlink semiconductor inc. 16.0 glossary api application program interface atm asynchronous transfer mode cdp context descriptor protocol (the protocol used by zarlink?s mt9088x family of tdm-packet devices) cesop circuit emulation services over packet cesopsn circuit emulation services over packet switched networks context a programmed connection of a number of tdm ti meslots assembled into a unique packet stream. cpu central processing unit dma direct memory access dpll digital phase locked loop dsp digital signal processor gmii gigabit media independent interface h.100/h.110 high capacity tdm backplane standards h-mvip high-performance multi-vendor integrat ion protocol (a tdm bus standard) ietf internet engineering task force ia implementation agreement ip internet protocol (version 4, rfc 791, version 6, rfc 2460) jtag joint test algorithms group (generally used to refer to a standard way of providing a board-level test facility) l2tp layer 2 tunneling protocol (rfc 2661) lan local area network liu line interface unit mac media access control mef metro ethernet forum mfa mpls and frame relay alliance mii media independent interface mib management information base mpls multi protocol label switching mtie maximum time interval error mvip multi-vendor integration pr otocol (a tdm bus standard) pdh plesiochronous di gital hierarchy pll phase locked loop prs primary reference source prx packet receive pstn public switched telephone circuit zl50115/16/17/18/19/20 data sheet 93 zarlink semiconductor inc. ptx packet transmit pwe3 pseudo-wire emulation edge to edge (a working group of the ietf) qos quality of service rtp real time protocol (rfc 1889) pe protocol engine satop structure-agnostic tdm over packet st bus standard telecom bus, a standard interface for tdm data streams tdl tapped delay line tdm time division multiplexing udp user datagram protocol (rfc 768) ui unit interval vlan virtual local area network wfq weighted fair queuing c zarlink semiconductor 2003 all rights reserved. issue apprd. date acn 02 june 04 1 package code previous package codes www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at |
Price & Availability of ZL50120
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |